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[Qemu-devel] [PATCH v4 14/17] hw/intc/arm_gic: Add grouping support to g
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v4 14/17] hw/intc/arm_gic: Add grouping support to gic_update() |
Date: |
Fri, 1 May 2015 18:50:40 +0100 |
Add support to gic_update() for determining the current IRQ
and FIQ status when interrupt grouping is supported. This
simply requires that instead of always raising IRQ we
check the group of the highest priority pending interrupt
and the GICC_CTLR.FIQEn bit to see whether we should raise
IRQ or FIQ.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 6abdb14..c1d2e70 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -60,7 +60,7 @@ void gic_update(GICState *s)
int best_irq;
int best_prio;
int irq;
- int level;
+ int irq_level, fiq_level;
int cpu;
int cm;
@@ -70,6 +70,7 @@ void gic_update(GICState *s)
if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1))
|| !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) {
qemu_irq_lower(s->parent_irq[cpu]);
+ qemu_irq_lower(s->parent_fiq[cpu]);
return;
}
best_prio = 0x100;
@@ -83,15 +84,31 @@ void gic_update(GICState *s)
}
}
}
- level = 0;
+
+ irq_level = fiq_level = 0;
+
if (best_prio < s->priority_mask[cpu]) {
s->current_pending[cpu] = best_irq;
if (best_prio < s->running_priority[cpu]) {
- DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu);
- level = 1;
+ int group = GIC_TEST_GROUP(best_irq, cm);
+
+ if (extract32(s->ctlr, group, 1) &&
+ extract32(s->cpu_ctlr[cpu], group, 1)) {
+ if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) {
+ DPRINTF("Raised pending FIQ %d (cpu %d)\n",
+ best_irq, cpu);
+ fiq_level = 1;
+ } else {
+ DPRINTF("Raised pending IRQ %d (cpu %d)\n",
+ best_irq, cpu);
+ irq_level = 1;
+ }
+ }
}
}
- qemu_set_irq(s->parent_irq[cpu], level);
+
+ qemu_set_irq(s->parent_irq[cpu], irq_level);
+ qemu_set_irq(s->parent_fiq[cpu], fiq_level);
}
}
--
1.9.1
- [Qemu-devel] [PATCH v4 00/17] arm_gic: Add security and grouping support, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 17/17] hw/arm/highbank.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 16/17] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 15/17] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 14/17] hw/intc/arm_gic: Add grouping support to gic_update(),
Peter Maydell <=
- [Qemu-devel] [PATCH v4 02/17] hw/intc/arm_gic: Add Security Extensions property, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 11/17] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 10/17] hw/intc/arm_gic: Restrict priority view, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 08/17] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 09/17] hw/intc/arm_gic: Implement Non-secure view of RPR, Peter Maydell, 2015/05/01