Re: [Qemu-devel] [PATCH target-arm v6 07/14] net: cadence_gem: Split state struct and type into header

[Edgar E. Iglesias]

On Fri, Apr 24, 2015 at 01:28:45PM -0700, Peter Crosthwaite wrote:
> Create a new header for Cadence GEM to allow using the device with
> modern SoC programming conventions. The state struct needs to be
> visible to embed the device in SoC containers.
> 
> Reviewed-by: Alistair Francis <address@hidden>
> Reviewed-by: Peter Maydell <address@hidden>

Reviewed-by: Edgar E. Iglesias <address@hidden>


> Tested-by: Alistair Francis <address@hidden>
> Signed-off-by: Peter Crosthwaite <address@hidden>
> ---
> changed since v4:
> Added (c) information
> Make commit msg body self contained
> changed since v1:
> Fix /* Public */ comment spacing (Alistair review)
> 
>  hw/net/cadence_gem.c         | 43 +-------------------------
>  include/hw/net/cadence_gem.h | 73 
> ++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 74 insertions(+), 42 deletions(-)
>  create mode 100644 include/hw/net/cadence_gem.h
> 
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 5994306..dafe914 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -24,8 +24,7 @@
>  
>  #include <zlib.h> /* For crc32 */
>  
> -#include "hw/sysbus.h"
> -#include "net/net.h"
> +#include "hw/net/cadence_gem.h"
>  #include "net/checksum.h"
>  
>  #ifdef CADENCE_GEM_ERR_DEBUG
> @@ -141,8 +140,6 @@
>  #define GEM_DESCONF6      (0x00000294/4)
>  #define GEM_DESCONF7      (0x00000298/4)
>  
> -#define CADENCE_GEM_MAXREG        (0x00000640/4) /* Last valid GEM address */
> -
>  /*****************************************/
>  #define GEM_NWCTRL_TXSTART     0x00000200 /* Transmit Enable */
>  #define GEM_NWCTRL_TXENA       0x00000008 /* Transmit Enable */
> @@ -349,44 +346,6 @@ static inline void rx_desc_set_sar(unsigned *desc, int 
> sar_idx)
>      desc[1] |= R_DESC_1_RX_SAR_MATCH;
>  }
>  
> -#define TYPE_CADENCE_GEM "cadence_gem"
> -#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), 
> TYPE_CADENCE_GEM)
> -
> -typedef struct CadenceGEMState {
> -    SysBusDevice parent_obj;
> -
> -    MemoryRegion iomem;
> -    NICState *nic;
> -    NICConf conf;
> -    qemu_irq irq;
> -
> -    /* GEM registers backing store */
> -    uint32_t regs[CADENCE_GEM_MAXREG];
> -    /* Mask of register bits which are write only */
> -    uint32_t regs_wo[CADENCE_GEM_MAXREG];
> -    /* Mask of register bits which are read only */
> -    uint32_t regs_ro[CADENCE_GEM_MAXREG];
> -    /* Mask of register bits which are clear on read */
> -    uint32_t regs_rtc[CADENCE_GEM_MAXREG];
> -    /* Mask of register bits which are write 1 to clear */
> -    uint32_t regs_w1c[CADENCE_GEM_MAXREG];
> -
> -    /* PHY registers backing store */
> -    uint16_t phy_regs[32];
> -
> -    uint8_t phy_loop; /* Are we in phy loopback? */
> -
> -    /* The current DMA descriptor pointers */
> -    uint32_t rx_desc_addr;
> -    uint32_t tx_desc_addr;
> -
> -    uint8_t can_rx_state; /* Debug only */
> -
> -    unsigned rx_desc[2];
> -
> -    bool sar_active[4];
> -} CadenceGEMState;
> -
>  /* The broadcast MAC address: 0xFFFFFFFFFFFF */
>  static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF 
> };
>  
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> new file mode 100644
> index 0000000..f2e08e3
> --- /dev/null
> +++ b/include/hw/net/cadence_gem.h
> @@ -0,0 +1,73 @@
> +/*
> + * QEMU Cadence GEM emulation
> + *
> + * Copyright (c) 2011 Xilinx, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef CADENCE_GEM_H
> +
> +#define TYPE_CADENCE_GEM "cadence_gem"
> +#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), 
> TYPE_CADENCE_GEM)
> +
> +#include "net/net.h"
> +#include "hw/sysbus.h"
> +
> +#define CADENCE_GEM_MAXREG        (0x00000640/4) /* Last valid GEM address */
> +
> +typedef struct CadenceGEMState {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +
> +    /*< public >*/
> +    MemoryRegion iomem;
> +    NICState *nic;
> +    NICConf conf;
> +    qemu_irq irq;
> +
> +    /* GEM registers backing store */
> +    uint32_t regs[CADENCE_GEM_MAXREG];
> +    /* Mask of register bits which are write only */
> +    uint32_t regs_wo[CADENCE_GEM_MAXREG];
> +    /* Mask of register bits which are read only */
> +    uint32_t regs_ro[CADENCE_GEM_MAXREG];
> +    /* Mask of register bits which are clear on read */
> +    uint32_t regs_rtc[CADENCE_GEM_MAXREG];
> +    /* Mask of register bits which are write 1 to clear */
> +    uint32_t regs_w1c[CADENCE_GEM_MAXREG];
> +
> +    /* PHY registers backing store */
> +    uint16_t phy_regs[32];
> +
> +    uint8_t phy_loop; /* Are we in phy loopback? */
> +
> +    /* The current DMA descriptor pointers */
> +    uint32_t rx_desc_addr;
> +    uint32_t tx_desc_addr;
> +
> +    uint8_t can_rx_state; /* Debug only */
> +
> +    unsigned rx_desc[2];
> +
> +    bool sar_active[4];
> +} CadenceGEMState;
> +
> +#define CADENCE_GEM_H
> +#endif
> -- 
> 2.3.6.3.g2cc70ee
>