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Re: [Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC |
Date: |
Thu, 7 May 2015 15:07:07 +0100 |
On 6 May 2015 at 23:50, Peter Crosthwaite <address@hidden> wrote:
> Hi Peter and all,
>
> Xilinx's next gen SoC has been announced. This series adds a SoC and
> board.
>
> Series start with addition of ARM cortex A53 support (P1 and P2). The
> Soc skeleton is then added with GIC, EMACs and UARTs added. The
> pre-existing models for GEM and UART are not SoC friendly (no visible
> state struct), so those are refactored for SoC.
>
> Create a model of the EP108 board. Currently this doesn't have any
> EP108 specific features but is a usable board exposing the user visible
> features of the raw SoC.
>
> See individual patches for detailed change logs.
>
> changed since v6 (Edgar review):
> Added GIC region size macro
> Added GIC alises
I've made some comments about these new GIC bits. Other than that
I don't have any problem with the rest of the series (though I haven't
actually reviewed all the patches, I'm happy not to :-))
thanks
-- PMM
- [Qemu-devel] [PATCH target-arm v7 08/15] net: cadence_gem: Split state struct and type into header, (continued)
- [Qemu-devel] [PATCH target-arm v7 08/15] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 15/15] arm: xlnx-ep108: Add bootloading, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 11/15] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 09/15] arm: xlnx-zynqmp: Add GEM support, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 14/15] arm: xlnx-ep108: Add external RAM, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 07/15] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 01/15] target-arm: cpu64: generalise name of A57 regs, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 10/15] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 12/15] arm: xlnx-zynqmp: Add UART support, Peter Crosthwaite, 2015/05/06
- Re: [Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC,
Peter Maydell <=