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[Qemu-devel] [PULL 19/19] hw/arm/highbank.c: Wire FIQ between CPU <> GIC
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/19] hw/arm/highbank.c: Wire FIQ between CPU <> GIC |
Date: |
Mon, 11 May 2015 14:40:38 +0100 |
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/arm/highbank.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index b2d048b..f8353a7 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -217,6 +217,7 @@ static void calxeda_init(MachineState *machine, enum
cxmachines machine_id)
qemu_irq pic[128];
int n;
qemu_irq cpu_irq[4];
+ qemu_irq cpu_fiq[4];
MemoryRegion *sysram;
MemoryRegion *dram;
MemoryRegion *sysmem;
@@ -269,6 +270,7 @@ static void calxeda_init(MachineState *machine, enum
cxmachines machine_id)
exit(1);
}
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
+ cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
}
sysmem = get_system_memory();
@@ -313,6 +315,7 @@ static void calxeda_init(MachineState *machine, enum
cxmachines machine_id)
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
+ sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
}
for (n = 0; n < 128; n++) {
--
1.9.1
- [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 03/19] hw/intc/arm_gic: Create outbound FIQ lines, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 09/19] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 06/19] hw/intc/arm_gic: Add Interrupt Group Registers, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 04/19] hw/intc/arm_gic: Add Security Extensions property, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 08/19] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 19/19] hw/arm/highbank.c: Wire FIQ between CPU <> GIC,
Peter Maydell <=
- [Qemu-devel] [PULL 10/19] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 17/19] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 16/19] hw/intc/arm_gic: Add grouping support to gic_update(), Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 11/19] hw/intc/arm_gic: Implement Non-secure view of RPR, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 15/19] hw/intc/arm_gic: Change behavior of IAR writes, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 07/19] hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 14/19] hw/intc/arm_gic: Change behavior of EOIR writes, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 01/19] armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE bit is set, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 13/19] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 18/19] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/11