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[Qemu-devel] How qemu performs CMOVcc instruction in target-i386/transla

From: Pang Wing
Subject: [Qemu-devel] How qemu performs CMOVcc instruction in target-i386/translate.c?
Date: Tue, 12 May 2015 09:51:24 +0800


I'm still trying to understanding how disas_insn in target-i386/translate.c works.

Currently I met "case 0x140 ... 0x14f: /* cmov Gv, Ev */",

I thought it just check the condition and execute the MOV according to the condition.

However, in gen_cmovcc1 function, I have no idea where the condition checks.

It seems to load source value (register or memory) into cpu_T[0] by "gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);", and I have no idea what "CCPrepare cc;" doing, but I thought 

    tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
                       cpu_T[0], cpu_regs[reg]);
    gen_op_mov_reg_v(ot, reg, cpu_T[0]);

will give some hints.

gen_op_mov_reg_v function looks simply move the result into the destination register, so I thought the condition checking is performed in tcg_gen_movcond_tl function.

When look into tcg_gen_movcond_tl function, I found it defined in tcg-op.h, which:

#define tcg_gen_movcond_tl tcg_gen_movcond_i32

and in tcg_gen_movcond_i32, because I target on i386, TCG_TARGET_HAS_movcond_i32 should be 1 and this function only execute:

    tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);

I really have no idea what tcg_gen_op6i_i32 doing, the argument naming is helpless (arg1 to arg6).

Did I track the wrong way?

I really appreciate any help you can provide.


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