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[Qemu-devel] [PATCH v1 15/18] target-arm: Add CNTHCTL_EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 15/18] target-arm: Add CNTHCTL_EL2 |
Date: |
Wed, 13 May 2015 16:52:40 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 33 +++++++++++++++++++++++++++++++--
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 73a4ce8..059c200 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -355,6 +355,7 @@ typedef struct CPUARMState {
};
uint64_t c14_cntfrq; /* Counter Frequency register */
uint64_t c14_cntkctl; /* Timer Control register */
+ uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 380887a..4c1d6c7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1155,8 +1155,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env,
const ARMCPRegInfo *ri)
static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
{
+ unsigned int cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
+ !extract32(env->cp15.cnthctl_el2, 0, 1)) {
+ env->exception.target_el = 2;
+ return CP_ACCESS_TRAP;
+ }
+
/* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
- if (arm_current_el(env) == 0 &&
+ if (cur_el == 0 &&
!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
env->exception.target_el = 1;
return CP_ACCESS_TRAP;
@@ -1166,10 +1176,21 @@ static CPAccessResult gt_counter_access(CPUARMState
*env, int timeridx)
static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
{
+ unsigned int cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ if (timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
+ !extract32(env->cp15.cnthctl_el2, 1, 1)) {
+ env->exception.target_el = 2;
+ return CP_ACCESS_TRAP;
+ }
+ }
+
/* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
* EL0[PV]TEN is zero.
*/
- if (arm_current_el(env) == 0 &&
+ if (cur_el == 0 &&
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
env->exception.target_el = 1;
return CP_ACCESS_TRAP;
@@ -2571,6 +2592,10 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
.opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 13, .crm = 0,
.access = PL2_RW,
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
+ { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ .access = PL2_RW,
+ .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, },
{ .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW,
@@ -2684,6 +2709,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
.access = PL2_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
#ifndef CONFIG_USER_ONLY
+ { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
{ .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW,
--
1.9.1
- [Qemu-devel] [PATCH v1 06/18] target-arm: Add TCR_EL2, (continued)
- [Qemu-devel] [PATCH v1 06/18] target-arm: Add TCR_EL2, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 07/18] target-arm: Add SCTLR_EL2, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 08/18] target-arm: Add TTBR0_EL2, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 09/18] target-arm: Add TLBI_ALLE1{IS}, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 10/18] target-arm: Add TLBIALLE2, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 11/18] target-arm: Add TPIDR_EL2, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 12/18] target-arm: Add TLBI_VAE2{IS}, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 13/18] target-arm: Add access to PAR_EL1, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 14/18] target-arm: Add CNTVOFF_EL2, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 15/18] target-arm: Add CNTHCTL_EL2,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 16/18] target-arm: Pass timeridx as argument to various timer functions, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 17/18] target-arm: Add HYP timer, Edgar E. Iglesias, 2015/05/13
- [Qemu-devel] [PATCH v1 18/18] hw/arm/virt: Connect the Hypervisor timer, Edgar E. Iglesias, 2015/05/13
- Re: [Qemu-devel] [PATCH v1 00/18] arm: Steps towards EL2 support round 3, Peter Maydell, 2015/05/18