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Re: [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transa

From: Paolo Bonzini
Subject: Re: [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transaction attributes
Date: Wed, 13 May 2015 13:36:10 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0

On 13/05/2015 13:21, Edgar E. Iglesias wrote:
> It was not clear to me if CPUs should hook into the iommu notification
> system or if we should make the iommu notification code signal changes
> through AS change notifications.
> The latter would be easy to get right I guess but we wouldn't be
> able to have any granularity in the flushing so performance could
> be better if the CPU somehow knows what parts have changed.

I think it's CPUs that should hook and flush their TLBs.


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