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[Qemu-devel] [PATCH v3 0/2] target-mips: Add support for misaligned acce

From: Yongbok Kim
Subject: [Qemu-devel] [PATCH v3 0/2] target-mips: Add support for misaligned accesses
Date: Wed, 13 May 2015 16:37:35 +0100

This patch set adds support for misaligned memory accesses in MIPS architecture
Release 6 and MIPS SIMD Architecture.

The behaviour, semantics, and architecture specifications of misaligned memory
accesses are described in:
MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS64
Architecture, Appendix B Misaligned Memory Accesses.
Available at http://www.imgtec.com/mips/architectures/mips64.asp


* Rewrote MSA patch
* Work-around is using byte-to-byte accesses and endianness corrections for 
  R5+MSA. (This replaces the misaligned flag from v2.) (Leon)
* Bug fixes (Leon)
* Separate helper functions for each data formats

* Removed re-translation in the mips_cpu_do_unaligned_access() (Peter)
* Checks validity only if an access is spanning into two pages in MSA (Leon)
* Introduced misaligned flag to indicate MSA ld/st is ongoing, is used to
  allow misaligned accesses in the mips_cpu_do_unaligned_access() callback.
  This is crucial to support MSA misaligned accesses in Release 5 cores.

Yongbok Kim (2):
  target-mips: Misaligned memory accesses for R6
  target-mips: Misaligned memory accesses for MSA

 target-mips/helper.h         |   10 ++-
 target-mips/op_helper.c      |  149 ++++++++++++++++++++++++-----------------
 target-mips/translate.c      |   23 +++++--
 target-mips/translate_init.c |    2 +-
 4 files changed, 112 insertions(+), 72 deletions(-)


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