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Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses

From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA
Date: Wed, 13 May 2015 14:31:46 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0

On 05/13/2015 01:59 PM, Leon Alrae wrote:
> On 13/05/15 20:58, Richard Henderson wrote:
>> On 05/13/2015 12:56 PM, Maciej W. Rozycki wrote:
>>>  We must have a way to deal with memory access operations issued by a 
>>> single machine instruction crossing a page boundary already as this is 
>>> what MIPS16 SAVE and RESTORE instructions as well as microMIPS SWP, SDP, 
>>> SWM, SDM, LWP, LDP, LWM and LDM ones do.  Perhaps these are worth 
>>> looking into and their approach copying (or reusing) here?
>> Certainly we do.  It's all in softmmu_template.h.
> I believe the problem is that MSA vector register's size is 16-bytes
> (this DATA_SIZE isn't supported in softmmu_template) and MSA load/store
> is supposed to be atomic.

What I meant is that the code to handle page boundary crosses is there in
softmmu_template.h.  If you want to copy that mechanism into the mips backend,
that's where you should start.


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