Re: [Qemu-devel] [PATCH v1 05/18] target-arm: Add MAIR_EL2

[Peter Maydell]

On 13 May 2015 at 07:52, Edgar E. Iglesias <address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
> ---
>  target-arm/helper.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d849b30..168549c 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2520,6 +2520,10 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = 
> {
>        .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
>        .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
>        .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
> +    { .name = "MAIR_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
> +      .access = PL2_RW,
> +      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

This has a 32-bit counterpart (which you can probably implement
via STATE_BOTH). Using ARM_CP_CONST is a better way to implement a
RAZ/WI register than providing read/write functions.

>      REGINFO_SENTINEL
>  };
>
> @@ -2595,6 +2599,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
>        .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
>        .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
> +    { .name = "MAIR_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
> +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, 
> cp15.mair_el[2]),
> +      .resetvalue = 0 },

Again, 32-bit counterpart.

>      REGINFO_SENTINEL
>  };

-- PMM