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[Qemu-devel] [PULL 04/10] target-tricore: add CMPSWP instructions of the
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA |
Date: |
Fri, 22 May 2015 17:06:02 +0200 |
Those instruction were introduced in the new Aurix platform.
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-tricore/translate.c | 35 +++++++++++++++++++++++++++++++++++
target-tricore/tricore-opcodes.h | 5 +++++
2 files changed, 40 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 1c37e48..06d183b 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -319,6 +319,20 @@ static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
tcg_temp_free(temp);
}
+static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
+{
+ TCGv temp = tcg_temp_new();
+ TCGv temp2 = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
+ cpu_gpr_d[reg], temp);
+ tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
+
+ tcg_temp_free(temp);
+ tcg_temp_free(temp2);
+}
+
/* We generate loads and store to core special function register (csfr) through
the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
makros R, A and E, which allow read-only, all and endinit protected access.
@@ -5046,6 +5060,18 @@ static void
decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_swap(ctx, r1, cpu_gpr_a[r2]);
break;
+ case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
+ tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ gen_cmpswap(ctx, r1, temp);
+ break;
+ case OPC2_32_BO_CMPSWAP_W_POSTINC:
+ gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ break;
+ case OPC2_32_BO_CMPSWAP_W_PREINC:
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
+ break;
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -5089,7 +5115,16 @@ static void
decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
gen_swap(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ case OPC2_32_BO_CMPSWAP_W_BR:
+ gen_cmpswap(ctx, r1, temp2);
+ gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ break;
+ case OPC2_32_BO_CMPSWAP_W_CIRC:
+ gen_cmpswap(ctx, r1, temp2);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ break;
}
+
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 2291f75..95837aa 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -763,6 +763,9 @@ enum {
OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
OPC2_32_BO_SWAP_W_POSTINC = 0x00,
OPC2_32_BO_SWAP_W_PREINC = 0x10,
+ OPC2_32_BO_CMPSWAP_W_SHORTOFF = 0x23,
+ OPC2_32_BO_CMPSWAP_W_POSTINC = 0x03,
+ OPC2_32_BO_CMPSWAP_W_PREINC = 0x13,
};
/*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
enum {
@@ -770,6 +773,8 @@ enum {
OPC2_32_BO_LDMST_CIRC = 0x11,
OPC2_32_BO_SWAP_W_BR = 0x00,
OPC2_32_BO_SWAP_W_CIRC = 0x10,
+ OPC2_32_BO_CMPSWAP_W_BR = 0x03,
+ OPC2_32_BO_CMPSWAP_W_CIRC = 0x13,
};
/*
* BRC Format
--
2.4.1
- [Qemu-devel] [PULL 00/10] tricore-patches, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 08/10] target-tricore: add FCALL instructions of the v1.6 ISA, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 02/10] target-tricore: introduce ISA v1.6.1 feature, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 06/10] target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 05/10] target-tricore: add SWAPMSK instructions of the v1.6.1 ISA, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 10/10] target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA, Bastian Koppelmann, 2015/05/22
- [Qemu-devel] [PULL 09/10] target-tricore: add FRET instructions of the v1.6 ISA, Bastian Koppelmann, 2015/05/22
- Re: [Qemu-devel] [PULL 00/10] tricore-patches, Peter Maydell, 2015/05/22