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[Qemu-devel] [PATCH 06/10] target-s390x: improve facilities list


From: Aurelien Jarno
Subject: [Qemu-devel] [PATCH 06/10] target-s390x: improve facilities list
Date: Mon, 25 May 2015 01:47:27 +0200

We currently use an hardcoded value for the STFL instruction. Move that
to a still hardcoded value but computed from bit values. This is more
maintainable and can be reused for the STFLE instruction.

Cc: Alexander Graf <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
 target-s390x/cpu.h       | 66 ++++++++++++++++++++++++++++++++++++++++++++++++
 target-s390x/translate.c |  4 +--
 2 files changed, 67 insertions(+), 3 deletions(-)

diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 99773e0..8bda2e0 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -165,6 +165,72 @@ typedef struct CPUS390XState {
 #include "cpu-qom.h"
 #include <sysemu/kvm.h>
 
+/* Facilities list */
+static const uint64_t facilities_dw[] = {
+    (1ULL << 63) | /* b 0: z/Architecture new instructions added to ESA/390 */
+    (1ULL << 62) | /* b 1: z/Architecture architectural */
+    (0ULL << 61) | /* b 2: z/Architecture architectural active */
+    (0ULL << 60) | /* b 3: IDTE */
+    (0ULL << 59) | /* b 4: IDTE selective clearing when segtab invalidated */
+    (0ULL << 58) | /* b 5: IDTE selective clearing when regtab invalidated */
+    (0ULL << 57) | /* b 6: ASN-and-LX-reuse facility */
+    (0ULL << 56) | /* b 7: Store-facility-list-extended facility */
+    (0ULL << 55) | /* b 8: Enhanced-DAT facility */
+    (0ULL << 54) | /* b 9: Sense-running-status facility */
+    (0ULL << 53) | /* b10: Conditional-SSKE facility */
+    (0ULL << 52) | /* b11: Configuration-topology facility */
+    (0ULL << 51) | /* b12: IBM internal use */
+    (0ULL << 50) | /* b13: IPTE-Range facility */
+    (0ULL << 49) | /* b14: Nonquiescing key-setting facility */
+    (0ULL << 48) | /* b15: IBM internal use */
+    (0ULL << 47) | /* b16: Extended-translation facility 2 */
+    (0ULL << 46) | /* b17: Message-security assist */
+    (0ULL << 45) | /* b18: Long-displacement facility */
+    (0ULL << 44) | /* b19: High performance long-displacement facility */
+    (0ULL << 43) | /* b20: HFP-multiply-and-add/subtract facility */
+    (0ULL << 42) | /* b21: Extended-immediate facility */
+    (0ULL << 41) | /* b22: Extended-translation facility 3 */
+    (0ULL << 40) | /* b23: HFP-unnormalized-extension facility */
+    (0ULL << 39) | /* b24: ETF2-enhancement facility */
+    (0ULL << 38) | /* b25: Store-clock-fast facility */
+    (0ULL << 37) | /* b26: Parsing-enhancement facility */
+    (0ULL << 36) | /* b27: Move-with-optional-specifications facility */
+    (0ULL << 35) | /* b28: TOD-clock-steering facility */
+    (0ULL << 33) | /* b30: ETF3-enhancement facility */
+    (0ULL << 32) | /* b31: Extract-CPU-time facility */
+    (0ULL << 31) | /* b32: Compare-and-swap-and-store facility */
+    (0ULL << 30) | /* b33: Compare-and-swap-and-store facility 2 */
+    (0ULL << 29) | /* b34: General-instructions-extension facility */
+    (0ULL << 28) | /* b35: Execute-extensions facility  */
+    (0ULL << 27) | /* b36: Enhanced-monitor facility */
+    (0ULL << 26) | /* b37: Floating-point extension facility */
+    (0ULL << 24) | /* b39: IBM internal use */
+    (0ULL << 23) | /* b40: Set-program-parameters facility */
+    (0ULL << 22) | /* b41: Floating-point-support-enhancement facilities */
+    (0ULL << 21) | /* b42: DFP facility */
+    (0ULL << 20) | /* b43: High performance DFP facility */
+    (0ULL << 19) | /* b44: PFPO instruction */
+    (0ULL << 18) | /* b45: Fast-BCR-serialization facility */
+    (0ULL << 17) | /* b46: IBM internal use */
+    (0ULL << 16) | /* b47: CMPSC-enhancement facility */
+    (0ULL << 15) | /* b48: DFP zoned-conversion facility */
+    (0ULL << 14) | /* b49: Execution-hint, load-and-trap facility */
+    (0ULL << 13) | /* b50: Transactional-execution facility */
+    (0ULL << 12) | /* b51: Local-TLB-clearing facility */
+    (0ULL << 11) | /* b52: interlocked-access facility 2 */
+    (0ULL <<  1) | /* b62: IBM internal use */
+    (0ULL <<  0)   /* b63: IBM internal use */
+,
+    (0ULL << 61) | /* b66: Reset-reference-bits-multiple facility */
+    (0ULL << 60) | /* b67: CPU-measurement counter facility */
+    (0ULL << 59) | /* b68: CPU-measurement sampling facility */
+    (0ULL << 54) | /* b73: Transactional-execution facility in zArch */
+    (0ULL << 52) | /* b75: Access-exception-fetch/store-indication facility */
+    (0ULL << 51) | /* b76: Message-security-assist-extension-3 facility */
+    (0ULL << 50) | /* b77: Message-security-assist-extension-4 facility */
+    (0ULL << 49)   /* b78: Enhanced-DAT facility 2 */
+};
+
 /* distinguish between 24 bit and 31 bit addressing */
 #define HIGH_ORDER_BIT 0x80000000
 
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 745195f..542da53 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -3373,10 +3373,8 @@ static ExitStatus op_spt(DisasContext *s, DisasOps *o)
 static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
 {
     TCGv_i64 f, a;
-    /* We really ought to have more complete indication of facilities
-       that we implement.  Address this when STFLE is implemented.  */
     check_privileged(s);
-    f = tcg_const_i64(0xc0000000);
+    f = tcg_const_i64(facilities_dw[0] >> 32);
     a = tcg_const_i64(200);
     tcg_gen_qemu_st32(f, a, get_mem_index(s));
     tcg_temp_free_i64(f);
-- 
2.1.4




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