[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [SeaBIOS] [PATCH 2/3] target-i386: reserve RCRB mmio sp

From: Paulo Alcantara
Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH 2/3] target-i386: reserve RCRB mmio space in ACPI DSDT table
Date: Sat, 30 May 2015 07:57:29 -0300

Hi Gerd,

On Thu, 28 May 2015 09:13:35 +0200
Gerd Hoffmann <address@hidden> wrote:

> > +Scope(\_SB) {
> > +    OperationRegion (RCRB, SystemMemory, 0xfed1c000, 0x4000)
> Where does this address come from?

This address is reserved in an ACPI DSDT table for Intel Haswell in
Coreboot project, Vlv2DeviceRefCodePkg package in EDK II as well as my
Haswell laptop on which I can see it through `dmesg` :-)

> Is this a standard location suggested by intel specs?

I haven't found any Intel spec or any other document that suggests such
address, but from "9.4 Memory Map" section in ICH9 spec, it seems safe
to use that MMIO region for the 16KiB of chipset configuration

> Or is the firmware free to choose it?

Given that, I would say so.



Paulo Alcantara, C.E.S.A.R
Speaking for myself only.

reply via email to

[Prev in Thread] Current Thread [Next in Thread]