[Qemu-devel] [RFC v2 25/34] arm: enable multi-arch

[Peter Crosthwaite]

Multi-arch conversion consisting of:
 * configury
    - defining CONFIG_ARCH_MULTI
    - adding to MULTI_TARGETS
    - enabling disas for MULTI_ARCH
 * Converting target-arm to arch-obj-y
 * cpu.h
   - Compiling out all target-arm private contents
     when doing multi-arch build
   - Redefining target_ulong and cpu-def typenames with arch prefix
   - Undeffing possibly previously defined macros
 * Defining the QOM cpu hooks

Signed-off-by: Peter Crosthwaite <address@hidden>
---
I guess I could split to multi patches but it will bloat this series!
---
 configure                |  8 ++++++-
 target-arm/Makefile.objs | 24 +++++++++----------
 target-arm/cpu-qom.h     |  2 ++
 target-arm/cpu.c         |  1 +
 target-arm/cpu.h         | 60 ++++++++++++++++++++++++++++++++++++++++++++++--
 5 files changed, 80 insertions(+), 15 deletions(-)

diff --git a/configure b/configure
index 3dbfd3e..353d323 100755
--- a/configure
+++ b/configure
@@ -5408,9 +5408,15 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
   arm|aarch64)
     echo "CONFIG_ARM_DIS=y"  >> $config_target_mak
     echo "CONFIG_ARM_DIS=y"  >> config-all-disas.mak
+    if [ -e $config_target_multi_mak ]; then
+        echo "CONFIG_ARM_DIS=y"  >> $config_target_multi_mak
+    fi
     if test -n "${cxx}"; then
       echo "CONFIG_ARM_A64_DIS=y"  >> $config_target_mak
       echo "CONFIG_ARM_A64_DIS=y"  >> config-all-disas.mak
+      if [ -e $config_target_multi_mak ]; then
+        echo "CONFIG_ARM_A64_DIS=y"  >> $config_target_multi_mak
+      fi
     fi
   ;;
   cris)
@@ -5484,7 +5490,7 @@ if test "$tcg_interpreter" = "yes" ; then
 fi
 
 case "$TARGET_BASE_ARCH" in
-microblaze)
+microblaze|arm)
   echo "CONFIG_ARCH_MULTI=y" >> $config_target_mak
 ;;
 *)
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index 9460b40..5725c57 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -1,12 +1,12 @@
-obj-y += arm-semi.o
-obj-$(CONFIG_SOFTMMU) += machine.o
-obj-$(CONFIG_KVM) += kvm.o
-obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
-obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
-obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
-obj-y += translate.o op_helper.o helper.o cpu.o
-obj-y += neon_helper.o iwmmxt_helper.o
-obj-y += gdbstub.o
-obj-$(CONFIG_SOFTMMU) += psci.o
-obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
-obj-y += crypto_helper.o
+arch-obj-y += arm-semi.o
+arch-obj-$(CONFIG_SOFTMMU) += machine.o
+arch-obj-$(CONFIG_KVM) += kvm.o
+arch-obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
+arch-obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
+arch-obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
+arch-obj-y += translate.o op_helper.o helper.o cpu.o
+arch-obj-y += neon_helper.o iwmmxt_helper.o
+arch-obj-y += gdbstub.o
+arch-obj-$(CONFIG_SOFTMMU) += psci.o
+arch-obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
+arch-obj-y += crypto_helper.o
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index ed5a644..7204116 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -188,9 +188,11 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
     return container_of(env, ARMCPU, env);
 }
 
+#ifndef TARGET_MULTI
 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
 
 #define ENV_OFFSET offsetof(ARMCPU, env)
+#endif /* !TARGET_MULTI */
 
 #ifndef CONFIG_USER_ONLY
 extern const struct VMStateDescription vmstate_arm_cpu;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index f135529..4210cd4 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -401,6 +401,7 @@ static void arm_cpu_initfn(Object *obj)
     ARMCPU *cpu = ARM_CPU(obj);
     static bool inited;
 
+    CPU_SET_QOM_HOOKS(cs);
     cs->env_ptr = &cpu->env;
     cpu_exec_init(cs);
     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 99a6c7e..3d55343 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -23,6 +23,7 @@
 
 #include "kvm-consts.h"
 
+#undef TARGET_LONG_BITS
 #if defined(TARGET_AARCH64)
   /* AArch64 definitions */
 #  define TARGET_LONG_BITS 64
@@ -34,13 +35,26 @@
 
 #define TARGET_IS_BIENDIAN 1
 
+#undef CPUArchState
 #define CPUArchState struct CPUARMState
 
 #include "qemu-common.h"
+
+#undef CPUTLBEntry
+#undef CPUIOTLBEntry
+#undef target_long
+#undef target_ulong
+#define CPUTLBEntry ARMCPUTLBEntry
+#define CPUIOTLBEntry ARMCPUIOTLBEntry
+#define target_long arm_target_long
+#define target_ulong arm_target_ulong
+
 #include "exec/cpu-defs.h"
 
 #include "fpu/softfloat.h"
 
+#ifndef TARGET_MULTI
+
 #define EXCP_UDEF            1   /* undefined instruction */
 #define EXCP_SWI             2   /* software interrupt */
 #define EXCP_PREFETCH_ABORT  3
@@ -57,6 +71,10 @@
 #define EXCP_VIRQ           14
 #define EXCP_VFIQ           15
 
+#endif /* TARGET_MULTI */
+
+/* These defs are public as needed by ARMv7M NVIC */
+
 #define ARMV7M_EXCP_RESET   1
 #define ARMV7M_EXCP_NMI     2
 #define ARMV7M_EXCP_HARD    3
@@ -73,6 +91,8 @@
 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
 
+#ifndef TARGET_MULTI
+
 /* The usual mapping for an AArch64 system register to its AArch32
  * counterpart is for the 32 bit world to have access to the lower
  * half only (with writes leaving the upper half untouched). It's
@@ -87,6 +107,8 @@
 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
 #endif
 
+#endif /* !TARGET_MULTI */
+
 /* Meanings of the ARMCPU object's four inbound GPIO lines */
 #define ARM_CPU_IRQ 0
 #define ARM_CPU_FIQ 1
@@ -95,6 +117,7 @@
 
 struct arm_boot_info;
 
+#undef NB_MMU_MODES
 #define NB_MMU_MODES 7
 
 /* We currently assume float and double are IEEE single and double
@@ -492,6 +515,8 @@ static inline ARMCPU *cpu_arm_init(const char *cpu_model)
     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
 }
 
+#ifndef TARGET_MULTI
+
 int cpu_arm_exec(CPUState *cpu);
 uint32_t do_arm_semihosting(CPUARMState *env);
 void aarch64_sync_32_to_64(CPUARMState *env);
@@ -624,6 +649,12 @@ void pmccntr_sync(CPUARMState *env);
 #define TTBCR_SH1    (1U << 28)
 #define TTBCR_EAE    (1U << 31)
 
+#endif /* !TARGET_MULTI */
+
+/* Some bits of system level code do direct deposit to the PSTATE. Allow
+ * these symbols as global even in multi-arch.
+ */
+
 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
  * Only these are valid when in AArch64 mode; in
  * AArch32 mode SPSRs are basically CPSR-format.
@@ -653,6 +684,8 @@ void pmccntr_sync(CPUARMState *env);
 #define PSTATE_MODE_EL1t 4
 #define PSTATE_MODE_EL0t 0
 
+#ifndef TARGET_MULTI
+
 /* Map EL and handler into a PSTATE_MODE.  */
 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
 {
@@ -761,7 +794,13 @@ static inline void xpsr_write(CPUARMState *env, uint32_t 
val, uint32_t mask)
 #define HCR_ID        (1ULL << 33)
 #define HCR_MASK      ((1ULL << 34) - 1)
 
+#endif /* !TARGET_MULTI */
+
+/* bootloader needs this to init security state of processor */
 #define SCR_NS                (1U << 0)
+
+#ifndef TARGET_MULTI
+
 #define SCR_IRQ               (1U << 1)
 #define SCR_FIQ               (1U << 2)
 #define SCR_EA                (1U << 3)
@@ -810,6 +849,8 @@ static inline void vfp_set_fpcr(CPUARMState *env, uint32_t 
val)
     vfp_set_fpscr(env, new_fpscr);
 }
 
+#endif /* !TARGET_MULTI */
+
 enum arm_cpu_mode {
   ARM_CPU_MODE_USR = 0x10,
   ARM_CPU_MODE_FIQ = 0x11,
@@ -822,6 +863,8 @@ enum arm_cpu_mode {
   ARM_CPU_MODE_SYS = 0x1f
 };
 
+#ifndef TARGET_MULTI
+
 /* VFP system registers.  */
 #define ARM_VFP_FPSID   0
 #define ARM_VFP_FPSCR   1
@@ -842,6 +885,8 @@ enum arm_cpu_mode {
 #define ARM_IWMMXT_wCGR2       10
 #define ARM_IWMMXT_wCGR3       11
 
+#endif /* TARGET_MULTI */
+
 /* If adding a feature bit which corresponds to a Linux ELF
  * HWCAP bit, remember to update the feature-bit-to-hwcap
  * mapping in linux-user/elfload.c:get_elf_hwcap().
@@ -897,6 +942,8 @@ static inline int arm_feature(CPUARMState *env, int feature)
     return (env->features & (1ULL << feature)) != 0;
 }
 
+#ifndef TARGET_MULTI
+
 #if !defined(CONFIG_USER_ONLY)
 /* Return true if exception levels below EL3 are in secure state,
  * or would be following an exception return to that level.
@@ -1007,6 +1054,8 @@ static inline bool access_secure_reg(CPUARMState *env)
 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);
 
+#endif /* TARGET_MULTI */
+
 /* Interface between CPU and Interrupt controller.  */
 void armv7m_nvic_set_pending(void *opaque, int irq);
 int armv7m_nvic_acknowledge_irq(void *opaque);
@@ -1216,6 +1265,8 @@ static inline bool cptype_valid(int cptype)
 #define PL1_RW (PL1_R | PL1_W)
 #define PL0_RW (PL0_R | PL0_W)
 
+#ifndef TARGET_MULTI
+
 /* Return the current Exception Level (as per ARMv8; note that this differs
  * from the ARMv7 Privilege Level).
  */
@@ -1248,6 +1299,8 @@ static inline int arm_current_el(CPUARMState *env)
     }
 }
 
+#endif
+
 typedef struct ARMCPRegInfo ARMCPRegInfo;
 
 typedef enum CPAccessResult {
@@ -1429,6 +1482,8 @@ static inline bool cp_access_ok(int current_el,
     return (ri->access >> ((current_el * 2) + isread)) & 1;
 }
 
+#ifndef TARGET_MULTI
+
 /**
  * write_list_to_cpustate
  * @cpu: ARMCPU
@@ -1477,7 +1532,6 @@ bool write_cpustate_to_list(ARMCPU *cpu);
 /* ??? Linux doesn't actually use these, and they're deprecated in recent
    architecture revisions.  Maybe a configure option to disable them.  */
 #define TARGET_PAGE_BITS 10
-#endif
 
 #if defined(TARGET_AARCH64)
 #  define TARGET_PHYS_ADDR_SPACE_BITS 48
@@ -1486,6 +1540,7 @@ bool write_cpustate_to_list(ARMCPU *cpu);
 #  define TARGET_PHYS_ADDR_SPACE_BITS 40
 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
+#endif
 
 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
 {
@@ -1570,7 +1625,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, 
unsigned int excp_idx)
 
 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
 
-#define cpu_exec cpu_arm_exec
 #define cpu_gen_code cpu_arm_gen_code
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
@@ -1878,6 +1932,8 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, 
target_ulong *pc,
 
 #include "exec/exec-all.h"
 
+#endif /* !TARGET_MULTI */
+
 enum {
     QEMU_PSCI_CONDUIT_DISABLED = 0,
     QEMU_PSCI_CONDUIT_SMC = 1,
-- 
1.9.1