[Qemu-devel] [PATCH RFC V3 0/4] Implement GIC-500 from GICv3 family for arm64

[Shlomo Pongratz]

From: Shlomo Pongratz <address@hidden>

This patch is a first step toward 128 cores support for arm64.

At first only 64 cores are supported for two reasons:
First the largest integer type has the size of 64 bits and modifying
essential data structures in order to support 128 cores will require
the usage of bitops.
Second currently the Linux (kernel) can be configured to support
up to 64 cores thus there is no urgency with 128 cores support.

Things left to do:

There is a need to support flexible clusters size. The GIC-500 can support
up to 128 cores, up to 32 clusters and up to 8 cores is a cluster.
So for example, if one wishes to have 16 cores, the options are:
2 clusters of 8 cores each, 4 clusters with 4 cores each
Currently only the first option is supported.
There is an issue of passing clock affinity to via the dtb. In the dtb

interrupt section there are only 24 bit left to affinity since the
variable is a 32 bit entity and 8 bits are reserved for flags.
See Documentation/devicetree/bindings/arm/arch_timer.txt.
Note that this issue is not seems to be critical as when checking
/proc/irq/3/smp_affinity with 32 cores all 32 bits are one.

The last issue is to add support for 128 cores. This requires the usage
of bitops and currently can be tested up to 64 cores.

Special thanks to Peter Crostwaite whose patch to th Linux (kernel) i.e.
Implement cpu_relax as yield solved the problem of the boot process getting
stuck for 24 cores and more.

V2:
  - Split the original patch to 4 patches
  - Add SRE API to the GIC code.
  - Add call to gicv3_update to armv8_gicv3_set_priority_mask.
  - Cosmetic changes.
  - Fix number of irq when reading GICD_TYPER.

V3:
  - Replace my original 1 & 4 patches with Pavel's patches.
  - Add groups support to complies with new GICv2 addtions
  - Cosmetic changes.


Pavel Fedin (2):
  Use Aff1 with mpidr This is an improved and KVM-aware alternative to
  Add virt-v3 machine that uses GIC-500

Shlomo Pongratz (2):
  Implment GIC-500
  GICv3 support

 hw/arm/virt.c                      |  165 ++-
 hw/intc/Makefile.objs              |    2 +
 hw/intc/arm_gicv3.c                | 2086 ++++++++++++++++++++++++++++++++++++
 hw/intc/arm_gicv3_common.c         |  217 ++++
 hw/intc/gicv3_internal.h           |  161 +++
 include/hw/arm/virt.h              |    4 +
 include/hw/boards.h                |    1 +
 include/hw/intc/arm_gicv3.h        |   44 +
 include/hw/intc/arm_gicv3_common.h |  119 ++
 target-arm/cpu-qom.h               |    3 +
 target-arm/cpu.c                   |   17 +
 target-arm/cpu.h                   |   12 +
 target-arm/cpu64.c                 |  105 ++
 target-arm/helper.c                |    9 +-
 target-arm/kvm64.c                 |   25 +
 target-arm/psci.c                  |   20 +-
 16 files changed, 2952 insertions(+), 38 deletions(-)
 create mode 100644 hw/intc/arm_gicv3.c
 create mode 100644 hw/intc/arm_gicv3_common.c
 create mode 100644 hw/intc/gicv3_internal.h
 create mode 100644 include/hw/intc/arm_gicv3.h
 create mode 100644 include/hw/intc/arm_gicv3_common.h

-- 
1.9.1