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[Qemu-devel] [PULL 61/62] atomics: add explicit compiler fence in __atom
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 61/62] atomics: add explicit compiler fence in __atomic memory barriers |
Date: |
Fri, 5 Jun 2015 17:16:02 +0200 |
__atomic_thread_fence does not include a compiler barrier; in the
C++11 memory model, fences take effect in combination with other
atomic operations. GCC implements this by making __atomic_load and
__atomic_store access memory as if the pointer was volatile, and
leaves no trace whatsoever of acquire and release fences in the
compiler's intermediate representation.
In QEMU, we want memory barriers to act on all memory, but at the same
time we would like to use __atomic_thread_fence for portability reasons.
Add compiler barriers manually around the __atomic_thread_fence.
Message-Id: <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
include/qemu/atomic.h | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index 98e05ca..bd2c075 100644
--- a/include/qemu/atomic.h
+++ b/include/qemu/atomic.h
@@ -99,7 +99,13 @@
#ifndef smp_wmb
#ifdef __ATOMIC_RELEASE
-#define smp_wmb() __atomic_thread_fence(__ATOMIC_RELEASE)
+/* __atomic_thread_fence does not include a compiler barrier; instead,
+ * the barrier is part of __atomic_load/__atomic_store's "volatile-like"
+ * semantics. If smp_wmb() is a no-op, absence of the barrier means that
+ * the compiler is free to reorder stores on each side of the barrier.
+ * Add one here, and similarly in smp_rmb() and smp_read_barrier_depends().
+ */
+#define smp_wmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE);
barrier(); })
#else
#define smp_wmb() __sync_synchronize()
#endif
@@ -107,7 +113,7 @@
#ifndef smp_rmb
#ifdef __ATOMIC_ACQUIRE
-#define smp_rmb() __atomic_thread_fence(__ATOMIC_ACQUIRE)
+#define smp_rmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE);
barrier(); })
#else
#define smp_rmb() __sync_synchronize()
#endif
@@ -115,7 +121,7 @@
#ifndef smp_read_barrier_depends
#ifdef __ATOMIC_CONSUME
-#define smp_read_barrier_depends() __atomic_thread_fence(__ATOMIC_CONSUME)
+#define smp_read_barrier_depends() ({ barrier();
__atomic_thread_fence(__ATOMIC_CONSUME); barrier(); })
#else
#define smp_read_barrier_depends() barrier()
#endif
--
2.4.1
- [Qemu-devel] [PULL 51/62] hw/i386: add a separate region that tracks the SMRAME bit, (continued)
- [Qemu-devel] [PULL 51/62] hw/i386: add a separate region that tracks the SMRAME bit, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 53/62] hw/i386: remove smram_update, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 52/62] target-i386: use memory API to implement SMRAM, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 54/62] q35: implement high SMRAM, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 55/62] q35: fix ESMRAMC default, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 56/62] q35: add config space wmask for SMRAM and ESMRAMC, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 57/62] q35: implement SMRAM.D_LCK, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 58/62] q35: add test for SMRAM.D_LCK, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 60/62] ich9: implement SMI_LOCK, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 59/62] q35: implement TSEG, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 61/62] atomics: add explicit compiler fence in __atomic memory barriers,
Paolo Bonzini <=
- [Qemu-devel] [PULL 62/62] update Linux headers from kvm/next, Paolo Bonzini, 2015/06/05
- Re: [Qemu-devel] [PULL 00/62] KVM, dirty bitmap, build system, SMM, icount changes for 2015-06-05, Paolo Bonzini, 2015/06/05