[Qemu-devel] [PATCH pic32 5/7] Two new processor variants: M4K and microAptivP.

[Serge Vakulenko]

Signed-off-by: Serge Vakulenko <address@hidden>
---
 target-mips/cpu.h            |  2 ++
 target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index ab830ee..9f5890c 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -394,6 +394,7 @@ struct CPUMIPSState {
 #define CP0C0_M    31
 #define CP0C0_K23  28
 #define CP0C0_KU   25
+#define CP0C0_SB   21
 #define CP0C0_MDU  20
 #define CP0C0_MM   17
 #define CP0C0_BM   16
@@ -479,6 +480,7 @@ struct CPUMIPSState {
 #define CP0C5_NFExists   0
     int32_t CP0_Config6;
     int32_t CP0_Config7;
+#define CP0C7_WII        31
     /* XXX: Maybe make LLAddr per-TC? */
     uint64_t lladdr;
     target_ulong llval;
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index ddfaff8..430a547 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -232,6 +232,52 @@ static const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_FMT,
     },
     {
+        /* Configuration for Microchip PIC32MX microcontroller. */
+        .name = "M4K",
+        .CP0_PRid = 0x00018765,
+        .CP0_Config0 = MIPS_CONFIG0 | (2 << CP0C0_K23) | (2 << CP0C0_KU) |
+                       (1 << CP0C0_SB) | (1 << CP0C0_BM) |
+                       (1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
+        .CP0_Config1 = (1U << CP0C1_M) | (1 << CP0C1_CA) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = (1 << CP0C3_VEIC) | (1 << CP0C3_VInt),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1258FF17,
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+        .mmu_type = MMU_TYPE_FMT,
+    },
+    {
+        /* Configuration for Microchip PIC32MZ microcontroller. */
+        .name = "microAptivP",
+        .CP0_PRid = 0x00019e28,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+                    (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (1 << CP0C1_PC),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = (1 << CP0C3_M) | (1 << CP0C3_IPLW) | (1 << CP0C3_MCU) |
+                    (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+                    (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | (1 <<
CP0C3_VEIC) |
+                    (1 << CP0C3_VInt),
+        .CP0_Config4 = (1 << CP0C4_M),
+        .CP0_Config5 = (1 << CP0C5_NFExists),
+        .CP0_Config6 = 0,
+        .CP0_Config7 = (1 << CP0C7_WII),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1278FF17,
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS32R2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "24Kc",
         .CP0_PRid = 0x00019300,
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
--
1.9.1