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Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K an
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K and microAptivP. |
Date: |
Fri, 3 Jul 2015 23:04:36 +0100 (BST) |
User-agent: |
Alpine 2.11 (LFD 23 2013-08-11) |
On Wed, 1 Jul 2015, Aurelien Jarno wrote:
> > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> > index ddfaff8..430a547 100644
> > --- a/target-mips/translate_init.c
> > +++ b/target-mips/translate_init.c
> > @@ -232,6 +232,52 @@ static const mips_def_t mips_defs[] =
> > .mmu_type = MMU_TYPE_FMT,
> > },
> > {
> > + /* Configuration for Microchip PIC32MX microcontroller. */
> > + .name = "M4K",
> > + .CP0_PRid = 0x00018765,
Hmm, does it make sense to set the Revision field here? We keep it at 0
for other templates, so why not 0x00018700?
Also I suggest to move the template earlier on so that entries remain
sorted by PRId, at least within the same vendor. So this would go between
"4KEmR1" and "4KEc" (the M4K is an MTI RTL, quite an old one actually).
> > + {
> > + /* Configuration for Microchip PIC32MZ microcontroller. */
> > + .name = "microAptivP",
> > + .CP0_PRid = 0x00019e28,
Same question here, why not 0x00019e00? Also why not "microAptivUP" as
documentation calls it (vs "microAptivUC")?
And again, it looks to me like the entry better followed "M14Kc".
> Otherwise it looks ok, though I haven't look at the PIC32 manual to
> check the values.
I haven't checked if the bit patterns for configuration registers are
sane either. These RTLs are configurable, so (within some limits) real
hardware will have different values anyway.
Maciej
- Re: [Qemu-devel] [PATCH pic32 v2 1/5] Speed of MIPS CPU timer made configurable per platform., (continued)
Message not available
- [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode., Serge Vakulenko, 2015/07/01
- Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode., Aurelien Jarno, 2015/07/01
- Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode., Serge Vakulenko, 2015/07/05
- Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode., Serge Vakulenko, 2015/07/05
- Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode., Aurelien Jarno, 2015/07/06
Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode., Aurelien Jarno, 2015/07/06
Message not available
Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K and microAptivP., Serge Vakulenko, 2015/07/05
Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K and microAptivP., Aurelien Jarno, 2015/07/06
Message not available
- [Qemu-devel] [PATCH pic32 v2 5/5] Two new machine platforms: pic32mz7 and pic32mz., Serge Vakulenko, 2015/07/01
- Re: [Qemu-devel] [PATCH pic32 v2 5/5] Two new machine platforms: pic32mz7 and pic32mz., Aurelien Jarno, 2015/07/01
- Re: [Qemu-devel] [PATCH pic32 v2 5/5] Two new machine platforms: pic32mz7 and pic32mz., Serge Vakulenko, 2015/07/06
- Re: [Qemu-devel] [PATCH pic32 v2 5/5] Two new machine platforms: pic32mz7 and pic32mz., Antony Pavlov, 2015/07/06
- Re: [Qemu-devel] [PATCH pic32 v2 5/5] Two new machine platforms: pic32mz7 and pic32mz., Serge Vakulenko, 2015/07/06
- Re: [Qemu-devel] [PATCH pic32 v2 5/5] Two new machine platforms: pic32mz7 and pic32mz., Peter Crosthwaite, 2015/07/06
- Re: [Qemu-devel] [PATCH pic32 v2 5/5] Two new machine platforms: pic32mz7 and pic32mz., Antony Pavlov, 2015/07/07