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Re: [Qemu-devel] [PATCH v10 11/21] i.MX: Split GPT emulator in a header
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v10 11/21] i.MX: Split GPT emulator in a header file and a source file |
Date: |
Sun, 5 Jul 2015 23:51:24 -0700 |
On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
<address@hidden> wrote:
> Signed-off-by: Jean-Christophe Dubois <address@hidden>
> ---
>
> Changes since v1:
> * not present on v1
>
> Changes since v2:
> * not present on v2
>
> Changes since v3:
> * not present on v3
>
> Changes since v4:
> * not present on v4
>
> Changes since v5:
> * not present on v5
>
> Changes since v6:
> * not present on v6
>
> Changes since v7:
> * Splited the i.MX GPT emulator into a header file and a source file
>
> Changes since v8:
> * no change
>
> Changes since v9:
> * no change
>
> hw/timer/imx_gpt.c | 79 ++-------------------------------
> include/hw/timer/imx_gpt.h | 107
> +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 110 insertions(+), 76 deletions(-)
> create mode 100644 include/hw/timer/imx_gpt.h
>
> diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
> index 3b31010..f61d4e5 100644
> --- a/hw/timer/imx_gpt.c
> +++ b/hw/timer/imx_gpt.c
> @@ -5,23 +5,18 @@
> * Copyright (c) 2011 NICTA Pty Ltd
> * Originally written by Hans Jiang
> * Updated by Peter Chubb
> - * Updated by Jean-Christophe Dubois
> + * Updated by Jean-Christophe Dubois <address@hidden>
> *
> * This code is licensed under GPL version 2 or later. See
> * the COPYING file in the top-level directory.
> *
> */
>
> -#include "hw/hw.h"
> -#include "qemu/bitops.h"
> -#include "qemu/timer.h"
> -#include "hw/ptimer.h"
> -#include "hw/sysbus.h"
> #include "hw/arm/imx.h"
> +#include "hw/timer/imx_gpt.h"
> +#include "hw/misc/imx_ccm.h"
> #include "qemu/main-loop.h"
>
> -#define TYPE_IMX_GPT "imx.gpt"
> -
> /*
> * Define to 1 for debug messages
> */
> @@ -74,74 +69,6 @@ static char const *imx_gpt_reg_name(uint32_t reg)
> # define IPRINTF(fmt, args...) do {} while (0)
> #endif
>
> -#define IMX_GPT(obj) \
> - OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
> -/*
> - * GPT : General purpose timer
> - *
> - * This timer counts up continuously while it is enabled, resetting itself
> - * to 0 when it reaches GPT_TIMER_MAX (in freerun mode) or when it
> - * reaches the value of one of the ocrX (in periodic mode).
> - */
> -
> -#define GPT_TIMER_MAX 0XFFFFFFFFUL
> -
> -/* Control register. Not all of these bits have any effect (yet) */
> -#define GPT_CR_EN (1 << 0) /* GPT Enable */
> -#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
> -#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
> -#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
> -#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
> -#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
> -#define GPT_CR_CLKSRC_SHIFT (6)
> -#define GPT_CR_CLKSRC_MASK (0x7)
> -
> -#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
> -#define GPT_CR_SWR (1 << 15) /* Software Reset */
> -#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
> -#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
> -#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
> -#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
> -#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
> -#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
> -#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
> -#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
> -
> -#define GPT_SR_OF1 (1 << 0)
> -#define GPT_SR_OF2 (1 << 1)
> -#define GPT_SR_OF3 (1 << 2)
> -#define GPT_SR_ROV (1 << 5)
> -
> -#define GPT_IR_OF1IE (1 << 0)
> -#define GPT_IR_OF2IE (1 << 1)
> -#define GPT_IR_OF3IE (1 << 2)
> -#define GPT_IR_ROVIE (1 << 5)
> -
> -typedef struct {
> - SysBusDevice busdev;
> - ptimer_state *timer;
> - MemoryRegion iomem;
> - DeviceState *ccm;
> -
> - uint32_t cr;
> - uint32_t pr;
> - uint32_t sr;
> - uint32_t ir;
> - uint32_t ocr1;
> - uint32_t ocr2;
> - uint32_t ocr3;
> - uint32_t icr1;
> - uint32_t icr2;
> - uint32_t cnt;
> -
> - uint32_t next_timeout;
> - uint32_t next_int;
> -
> - uint32_t freq;
> -
> - qemu_irq irq;
> -} IMXGPTState;
> -
> static const VMStateDescription vmstate_imx_timer_gpt = {
> .name = "imx.gpt",
> .version_id = 3,
> diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
> new file mode 100644
> index 0000000..e055951
> --- /dev/null
> +++ b/include/hw/timer/imx_gpt.h
> @@ -0,0 +1,107 @@
> +/*
> + * i.MX GPT Timer
> + *
> + * Copyright (c) 2008 OK Labs
> + * Copyright (c) 2011 NICTA Pty Ltd
> + * Originally written by Hans Jiang
> + * Updated by Peter Chubb
> + * Updated by Jean-Christophe Dubois <address@hidden>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef IMX_GPT_H
> +#define IMX_GPT_H
> +
> +#include "hw/sysbus.h"
> +#include "hw/ptimer.h"
> +
> +/*
> + * GPT : General purpose timer
> + *
> + * This timer counts up continuously while it is enabled, resetting itself
> + * to 0 when it reaches GPT_TIMER_MAX (in freerun mode) or when it
> + * reaches the value of one of the ocrX (in periodic mode).
> + */
> +
> +#define GPT_TIMER_MAX 0XFFFFFFFFUL
> +
> +/* Control register. Not all of these bits have any effect (yet) */
> +#define GPT_CR_EN (1 << 0) /* GPT Enable */
> +#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
> +#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
> +#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
> +#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
> +#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
> +#define GPT_CR_CLKSRC_SHIFT (6)
> +#define GPT_CR_CLKSRC_MASK (0x7)
> +
> +#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
> +#define GPT_CR_SWR (1 << 15) /* Software Reset */
> +#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
> +#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
> +#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
> +#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
> +#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
> +#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
> +#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
> +#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
> +
> +#define GPT_SR_OF1 (1 << 0)
> +#define GPT_SR_OF2 (1 << 1)
> +#define GPT_SR_OF3 (1 << 2)
> +#define GPT_SR_ROV (1 << 5)
> +
> +#define GPT_IR_OF1IE (1 << 0)
> +#define GPT_IR_OF2IE (1 << 1)
> +#define GPT_IR_OF3IE (1 << 2)
> +#define GPT_IR_ROVIE (1 << 5)
> +
> +#define TYPE_IMX_GPT "imx.gpt"
> +#define IMX_GPT(obj) OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
> +
> +typedef struct {
Keep IMXGPTState for double def.
> + /* <private> */
> + SysBusDevice parent_obj;
> +
> + /* <public> */
Spacing.
Otherwise:
Reviewed-by: Peter Crosthwaite <address@hidden>
Regards,
Peter
> + ptimer_state *timer;
> + MemoryRegion iomem;
> + DeviceState *ccm;
> +
> + uint32_t cr;
> + uint32_t pr;
> + uint32_t sr;
> + uint32_t ir;
> + uint32_t ocr1;
> + uint32_t ocr2;
> + uint32_t ocr3;
> + uint32_t icr1;
> + uint32_t icr2;
> + uint32_t cnt;
> +
> + uint32_t next_timeout;
> + uint32_t next_int;
> +
> + uint32_t freq;
> +
> + qemu_irq irq;
> +} IMXGPTState;
> +
> +#endif /* IMX_GPT_H */
> --
> 2.1.4
>
>
- [Qemu-devel] [PATCH v10 04/21] i.MX: Split AVIC emulator in a header file and a source file, (continued)
- [Qemu-devel] [PATCH v10 04/21] i.MX: Split AVIC emulator in a header file and a source file, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 05/21] i.MX: Fix Coding style for AVIC emulator., Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 07/21] i.MX: Fix Coding style for CCM emulator, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 06/21] i.MX: Split CCM emulator in a header file and a source file, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 08/21] i.MX: Split EPIT emulator in a header file and a source file, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 10/21] i.MX: Fix Coding style for EPIT emulator, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 09/21] i.MX: Move Qdev EPIT construction helper as inline function., Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 11/21] i.MX: Split GPT emulator in a header file and a source file, Jean-Christophe Dubois, 2015/07/05
- Re: [Qemu-devel] [PATCH v10 11/21] i.MX: Split GPT emulator in a header file and a source file,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v10 12/21] i.MX: Move Qdev GPT construction helper as inline function., Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 13/21] i.MX: Fix Coding style for GPT emulator, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 14/21] i.MX: Add SOC support for i.MX31, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 15/21] i.MX: KZM now uses the standalone i.MX31 SOC support, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 16/21] i.MX: Add I2C controller emulator, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 17/21] i.MX: Add FEC Ethernet Emulator, Jean-Christophe Dubois, 2015/07/05
- [Qemu-devel] [PATCH v10 18/21] i.MX: Add SOC support for i.MX25, Jean-Christophe Dubois, 2015/07/05