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[Qemu-devel] [PULL 1/7] target-arm: fix write helper for TLBI ALLE1IS
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 1/7] target-arm: fix write helper for TLBI ALLE1IS |
Date: |
Mon, 6 Jul 2015 10:59:29 +0100 |
From: Sergey Fedorov <address@hidden>
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.
Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aa34159..b87afe7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2441,7 +2441,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_write },
+ .writefn = tlbiall_is_write },
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW,
--
1.9.1
- [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 5/7] hw/intc/arm_gic_common.c: Reset all registers, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 3/7] target-arm: Split DISAS_YIELD from DISAS_WFE, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 1/7] target-arm: fix write helper for TLBI ALLE1IS,
Peter Maydell <=
- [Qemu-devel] [PULL 7/7] arm_mptimer: Respect IT bit state, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 6/7] arm_mptimer: Fix timer shutdown and mode change, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 4/7] target-arm: Implement YIELD insn to yield in ARM and Thumb translators, Peter Maydell, 2015/07/06
- [Qemu-devel] [PULL 2/7] Fix interval interrupt of cadence ttc when timer is in decrement mode, Peter Maydell, 2015/07/06
- Re: [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/07/06