[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 26/27] hw/cpu/a15mpcore: Wire up hyp and secure physi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/27] hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts |
Date: |
Thu, 13 Aug 2015 11:44:46 +0100 |
Since we now support both the hypervisor and the secure physical timer, wire
their interrupt lines up in the a15mpcore wrapper object.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
hw/cpu/a15mpcore.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index e31a1f9..58ac02e 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -75,14 +75,21 @@ static void a15mp_priv_realize(DeviceState *dev, Error
**errp)
for (i = 0; i < s->num_cpu; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = s->num_irq - 32 + i * 32;
- /* physical timer; we wire it up to the non-secure timer's ID,
- * since a real A15 always has TrustZone but QEMU doesn't.
+ int irq;
+ /* Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs used on the A15:
*/
- qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(gicdev, ppibase + 30));
- /* virtual timer */
- qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(gicdev, ppibase + 27));
+ const int timer_irq[] = {
+ [GTIMER_PHYS] = 30,
+ [GTIMER_VIRT] = 27,
+ [GTIMER_HYP] = 26,
+ [GTIMER_SEC] = 29,
+ };
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
+ qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(gicdev,
+ ppibase + timer_irq[irq]));
+ }
}
/* Memory map (addresses are offsets from PERIPHBASE):
--
1.9.1
- [Qemu-devel] [PULL 27/27] i.MX: Fix UART driver to work with unitialized "chardev" device, (continued)
- [Qemu-devel] [PULL 27/27] i.MX: Fix UART driver to work with unitialized "chardev" device, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 07/27] hw/arm/virt: Connect the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 11/27] i.MX: Split AVIC emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 03/27] target-arm: Rename and move gt_cnt_reset, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 13/27] i.MX: Split CCM emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 08/27] i.MX: Split UART emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 05/27] target-arm: Add the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 21/27] Introduce gic_class_name() instead of repeating condition, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 25/27] hw/arm/virt: Wire up secure timer interrupt, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 09/27] i.MX: Move serial initialization to init/realize of DeviceClass., Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 26/27] hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts,
Peter Maydell <=
- [Qemu-devel] [PULL 04/27] target-arm: Pass timeridx as argument to various timer functions, Peter Maydell, 2015/08/13
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/08/13