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[Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semih
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction |
Date: |
Thu, 13 Aug 2015 17:35:45 +0100 |
For the A64 instruction set, the semihosting call instruction
is 'HLT 0xf000'. Wire this up to call do_arm_semihosting()
if semihosting is enabled.
Signed-off-by: Peter Maydell <address@hidden>
---
linux-user/main.c | 3 +++
target-arm/cpu.h | 1 +
target-arm/helper-a64.c | 6 ++++++
target-arm/internals.h | 2 ++
target-arm/translate-a64.c | 14 ++++++++++++--
5 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index fdee981..56f452e 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1054,6 +1054,9 @@ void cpu_loop(CPUARMState *env)
queue_signal(env, info.si_signo, &info);
}
break;
+ case EXCP_SEMIHOST:
+ env->xregs[0] = do_arm_semihosting(env);
+ break;
default:
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index e067faa..fd91288 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -56,6 +56,7 @@
#define EXCP_SMC 13 /* Secure Monitor Call */
#define EXCP_VIRQ 14
#define EXCP_VFIQ 15
+#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 08c95a3..02fc9b4 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -514,6 +514,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
case EXCP_VFIQ:
addr += 0x100;
break;
+ case EXCP_SEMIHOST:
+ qemu_log_mask(CPU_LOG_INT,
+ "...handling as semihosting call 0x%" PRIx64 "\n",
+ env->xregs[0]);
+ env->xregs[0] = do_arm_semihosting(env);
+ return;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 924aff9..36a56aa 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -36,6 +36,7 @@ static inline bool excp_is_internal(int excp)
|| excp == EXCP_HALTED
|| excp == EXCP_EXCEPTION_EXIT
|| excp == EXCP_KERNEL_TRAP
+ || excp == EXCP_SEMIHOST
|| excp == EXCP_STREX;
}
@@ -58,6 +59,7 @@ static const char * const excnames[] = {
[EXCP_SMC] = "Secure Monitor Call",
[EXCP_VIRQ] = "Virtual IRQ",
[EXCP_VFIQ] = "Virtual FIQ",
+ [EXCP_SEMIHOST] = "Semihosting call",
};
static inline void arm_log_exception(int idx)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 689f2be..8810760 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -30,6 +30,7 @@
#include "internals.h"
#include "qemu/host-utils.h"
+#include "exec/semihost.h"
#include "exec/gen-icount.h"
#include "exec/helper-proto.h"
@@ -1553,8 +1554,17 @@ static void disas_exc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
break;
}
- /* HLT */
- unsupported_encoding(s, insn);
+ /* HLT. This has two purposes.
+ * Architecturally, it is an external halting debug instruction.
+ * Since QEMU doesn't implement external debug, we treat this as
+ * it is required for halting debug disabled: it will UNDEF.
+ * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
+ */
+ if (semihosting_enabled() && imm16 == 0xf000) {
+ gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
+ } else {
+ unsupported_encoding(s, insn);
+ }
break;
case 5:
if (op2_ll < 1 || op2_ll > 3) {
--
1.9.1
- [Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 2/9] target-arm: Improve semihosting debug prints, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 5/9] include/exec/softmmu-semi.h: Add support for 64-bit values, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 8/9] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction,
Peter Maydell <=
- [Qemu-devel] [PATCH 6/9] target-arm/arm-semi.c: Support widening APIs to 64 bits, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 3/9] gdbstub: Implement gdb_do_syscallv(), Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 1/9] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 7/9] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 4/9] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]', Peter Maydell, 2015/08/13