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Re: [Qemu-devel] [PATCH 0/5] Wire up various EL2/EL3 address translation
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 0/5] Wire up various EL2/EL3 address translation ops |
Date: |
Fri, 14 Aug 2015 11:10:14 +0100 |
Ping?
thanks
-- PMM
On 24 July 2015 at 16:20, Peter Maydell <address@hidden> wrote:
> This patch series wires up some of the EL2 and EL3 address
> translation operations which we were missing:
> * the AArch64 EL2 and EL3 AT ops
> * the AArch32 ATS12NSO ops
> * the AArch32 ATS1H ops
>
> Most of these are still not accessible or not very interesting
> because we don't have any CPUs which set ARM_FEATURE_EL2 yet.
> Providing ATS12NSO for AArch32-with-EL3 CPUs is a genuine bugfix.
>
> I included a bugfix for the 32-bit EL2 stage 1 translation
> regime. I think that the only remaining thing missing for EL2
> (based on eyeballing our current code) is implementing stage
> 2 translations.
>
> NB: this code isn't really tested, but it looks nice when you
> read it.
>
> Peter Maydell (5):
> target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
> target-arm: Wire up AArch64 EL2 and EL3 address translation ops
> target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2,3
> target-arm: Enable the AArch32 ATS12NSO ops
> target-arm: Implement AArch32 ATS1H* operations
>
> target-arm/cpu.h | 3 ++
> target-arm/helper.c | 88
> ++++++++++++++++++++++++++++++++++++++++++++++----
> target-arm/op_helper.c | 8 +++++
> 3 files changed, 92 insertions(+), 7 deletions(-)
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