[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops |
Date: |
Tue, 25 Aug 2015 16:00:07 +0100 |
Apply the correct conditions in the ats_access() function for
the ATS12NSO* address translation operations:
* succeed at EL2 or EL3
* normal UNDEF trap from NS EL1
* trap to EL3 from S EL1 (only possible if EL3 is AArch64)
(This change means they're now available in our EL3-supporting
CPUs when they would previously always UNDEF.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8603660..4b2fc090 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1719,12 +1719,17 @@ static void par_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (ri->opc2 & 4) {
- /* Other states are only available with TrustZone; in
- * a non-TZ implementation these registers don't exist
- * at all, which is an Uncategorized trap. This underdecoding
- * is safe because the reginfo is NO_RAW.
+ /* The ATS12NSO* operations must trap to EL3 if executed in
+ * Secure EL1 (which can only happen if EL3 is AArch64).
+ * They are simply UNDEF if executed from NS EL1.
+ * They function normally from EL2 or EL3.
*/
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ if (arm_current_el(env) == 1) {
+ if (arm_is_secure_below_el3(env)) {
+ return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
+ }
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
+ }
}
return CP_ACCESS_OK;
}
@@ -1899,6 +1904,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
offsetoflow32(CPUARMState, cp15.par_ns) },
.writefn = par_write },
#ifndef CONFIG_USER_ONLY
+ /* This underdecoding is safe because the reginfo is NO_RAW. */
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_W, .accessfn = ats_access,
.writefn = ats_write, .type = ARM_CP_NO_RAW },
--
1.9.1
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 19/20] target-arm: Implement missing EL3 TLB invalidate operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops,
Peter Maydell <=
- [Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 01/20] xlnx-zynqmp: Connect the four OCM banks, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 13/20] smbios: add smbios 3.0 support, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 14/20] smbios: implement smbios support for mach-virt, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 08/20] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 02/20] MAINTAINERS: Update Xilinx Maintainership, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 15/20] cputlb: Add functions for flushing TLB for a single MMU index, Peter Maydell, 2015/08/25