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[Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definition
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order |
Date: |
Tue, 25 Aug 2015 16:00:12 +0100 |
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6c55cc4..becc6f8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2701,14 +2701,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
.access = PL1_W, .type = ARM_CP_NOP },
/* TLBI operations */
- { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
- .access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_write },
- { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
- .access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_is_write },
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW,
@@ -2757,6 +2749,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
.access = PL1_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vaa_write },
+ { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbiall_is_write },
+ { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbiall_write },
#ifndef CONFIG_USER_ONLY
/* 64 bit address translation operations */
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
--
1.9.1
- [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops, (continued)
- [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 01/20] xlnx-zynqmp: Connect the four OCM banks, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order,
Peter Maydell <=
- [Qemu-devel] [PULL 13/20] smbios: add smbios 3.0 support, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 14/20] smbios: implement smbios support for mach-virt, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 08/20] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 02/20] MAINTAINERS: Update Xilinx Maintainership, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 15/20] cputlb: Add functions for flushing TLB for a single MMU index, Peter Maydell, 2015/08/25