[Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Petar Jovanovic]

From: Petar Jovanovic <address@hidden>

Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Signed-off-by: Petar Jovanovic <address@hidden>
---
v2:
- add check_cp1_registers() for recip.d and rsqrt.d, as suggested by Leon A.

 target-mips/translate.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 93cb4f2..15285bc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9294,7 +9294,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
         opn = "movn.s";
         break;
     case OPC_RECIP_S:
-        check_cop1x(ctx);
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
@@ -9306,7 +9305,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
         opn = "recip.s";
         break;
     case OPC_RSQRT_S:
-        check_cop1x(ctx);
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
@@ -9839,7 +9837,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
         opn = "movn.d";
         break;
     case OPC_RECIP_D:
-        check_cp1_64bitmode(ctx);
+        check_cp1_registers(ctx, fs | fd);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
@@ -9851,7 +9849,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
         opn = "recip.d";
         break;
     case OPC_RSQRT_D:
-        check_cp1_64bitmode(ctx);
+        check_cp1_registers(ctx, fs | fd);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
-- 
1.7.9.5