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Re: [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructio
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions |
Date: |
Sun, 30 Aug 2015 14:52:30 +0100 |
On 24 August 2015 at 17:17, Richard Henderson <address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target-tilegx/translate.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 51ee158..af4b34a 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -647,11 +647,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
> unsigned opext,
> case OE_RRR(FSINGLE_MUL2, 0, X0):
> case OE_RRR(FSINGLE_PACK2, 0, X0):
> case OE_RRR(FSINGLE_SUB1, 0, X0):
> + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RRR(MNZ, 0, X0):
> case OE_RRR(MNZ, 0, X1):
> case OE_RRR(MNZ, 4, Y0):
> case OE_RRR(MNZ, 4, Y1):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + t0 = load_zero(dc);
> + tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
> + mnemonic = "mnz";
> + break;
> case OE_RRR(MULAX, 0, X0):
> case OE_RRR(MULAX, 3, Y0):
> tcg_gen_mul_tl(tdest, tsrca, tsrcb);
> @@ -767,7 +771,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
> unsigned opext,
> case OE_RRR(MZ, 0, X1):
> case OE_RRR(MZ, 4, Y0):
> case OE_RRR(MZ, 4, Y1):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + t0 = load_zero(dc);
> + tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
> + mnemonic = "mz";
> + break;
> case OE_RRR(NOR, 0, X0):
> case OE_RRR(NOR, 0, X1):
> case OE_RRR(NOR, 5, Y0):
> --
> 2.4.3
>
I *think* this code is correct, but the ISA manual perplexes me
entirely. Why on earth would you describe anything as "compute
the boolean AND of something with a value of all ones", when that's
just a no-op? I can't see what I'm missing that means they
didn't just describe 'mz' as "dest = srcA ? srcB : 0".
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment load and store instructions, (continued)
- [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions, Richard Henderson, 2015/08/24
- Re: [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions,
Peter Maydell <=
- [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions, Richard Henderson, 2015/08/24