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Re: [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr |
Date: |
Sun, 30 Aug 2015 16:18:25 +0100 |
On 24 August 2015 at 17:17, Richard Henderson <address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target-tilegx/translate.c | 76
> +++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 73 insertions(+), 3 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 1224a8e..210e912 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -24,6 +24,7 @@
> #include "tcg-op.h"
> #include "exec/cpu_ldst.h"
> #include "opcode_tilegx.h"
> +#include "spr_def_64.h"
>
> #define FMT64X "%016" PRIx64
>
> @@ -1226,9 +1227,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc,
> unsigned opext,
> tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
> mnemonic = "ldna_add";
> break;
> - case OE_IM(MFSPR, X1):
> - case OE_IM(MTSPR, X1):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_IM(ORI, X0):
> case OE_IM(ORI, X1):
> tcg_gen_ori_tl(tdest, tsrca, imm);
> @@ -1528,6 +1526,74 @@ static TileExcp gen_jump_opcode_x1(DisasContext *dc,
> unsigned ext, int off)
> return TILEGX_EXCP_NONE;
> }
>
> +typedef struct {
> + const char *name;
> + intptr_t offset;
> + void (*get)(TCGv, TCGv_ptr);
> + void (*put)(TCGv_ptr, TCGv);
> +} TileSPR;
> +
> +static const TileSPR *find_spr(unsigned spr)
> +{
> + /* Allow the compiler to construct the binary search tree. */
This feels a bit overly clever to me but if we only have
three registers anyway it doesn't matter much.
> +#define D(N, O, G, P) \
> + case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; }
> +
> + switch (spr) {
> + D(CMPEXCH_VALUE,
> + offsetof(CPUTLGState, spregs[TILEGX_SPR_CMPEXCH]), 0, 0)
> + D(SIM_CONTROL,
> + offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
> + D(INTERRUPT_CRITICAL_SECTION,
> + offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
Aren't the offsets on these two backwards ?
> + }
> +
> +#undef D
> +
> + qemu_log_mask(LOG_UNIMP, "UNIMP SPR %u\n", spr);
> + return NULL;
> +}
-- PMM
- Re: [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions, (continued)
- [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr, Richard Henderson, 2015/08/24
- Re: [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr,
Peter Maydell <=
- [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h, Richard Henderson, 2015/08/24
- [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions, Richard Henderson, 2015/08/24
[Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui, Richard Henderson, 2015/08/24