Re: [Qemu-devel] [PATCH v2 1/2] target-mips: Use movcond in movci and movcf*

[Leon Alrae]

On 02/09/2015 23:50, Richard Henderson wrote:
> @@ -8821,102 +8840,126 @@ static void gen_cp1 (DisasContext *ctx, uint32_t 
> opc, int rt, int fs)
>      tcg_temp_free(t0);
>  }
>  
> -static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
> +static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
>  {
> -    TCGLabel *l1;
>      TCGCond cond;
> -    TCGv_i32 t0;
> +    TCGv t0, ts, zero;
>  
>      if (rd == 0) {
>          /* Treat as NOP. */
>          return;
>      }
>  
> -    if (tf)
> +    if (tf) {
>          cond = TCG_COND_EQ;
> -    else
> -        cond = TCG_COND_NE;
> -
> -    l1 = gen_new_label();
> -    t0 = tcg_temp_new_i32();
> -    tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
> -    tcg_gen_brcondi_i32(cond, t0, 0, l1);
> -    tcg_temp_free_i32(t0);
> -    if (rs == 0) {
> -        tcg_gen_movi_tl(cpu_gpr[rd], 0);
>      } else {
> -        tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
> +        cond = TCG_COND_NE;
>      }
> -    gen_set_label(l1);
> +
> +    t0 = tcg_temp_new();
> +    tcg_gen_extu_i32_tl(t0, fpu_fcr31);
> +    tcg_gen_andi_tl(t0, t0, 1 << get_fp_bit(cc));
> +
> +    zero = tcg_const_tl(0);
> +    ts = rs ? cpu_gpr[rs] : zero;
> +    tcg_gen_movcond_tl(cond, cpu_gpr[rd], t0, zero, ts, cpu_gpr[rd]);

MOVF and MOVT seem to do the opposite now, ts and cpu_gpr[rd] should be
swapped I think:

tcg_gen_movcond_tl(cond, cpu_gpr[rd], t0, zero, cpu_gpr[rd], ts);

Thanks,
Leon