Hi Mike,
On Thu, Sep 3, 2015 at 2:27 AM, GitNoviceMikeH
<address@hidden> wrote:
From: GitNoviceMikeH <address@hidden>
Most ARM cores switch unconditionally to ARM mode when an exception occurs;
a few (Cortex) variants have a "Thumb-exception enable" bit in the system
control register that allows an unconditional switch to Thumb mode instead
when handling exceptions. The presence of this bit seems unrelated to the
version of instruction set, so seems sensible to handle it as yet another
ARM feature?
What is the earliest ARM ARM the bit appears in?
---
target-arm/cpu.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 1 +
target-arm/helper.c | 11 ++++++++---
3 files changed, 64 insertions(+), 3 deletions(-)
...
+++ b/target-arm/helper.c
@@ -5658,11 +5658,16 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Switch to the new mode, and to the correct instruction set. */
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
env->daif |= mask;
- /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
- * and we should just guard the thumb mode on V4 */
- if (arm_feature(env, ARM_FEATURE_V4T)) {
+
+ /* Most ARM cores switch unconditionally to ARM mode when an exception
+ * occurs: */
/* comment style
* is like this
*/
Regards,
Peter
+ env->thumb = false;
+ /* ...but certain cores have a Thumb-exception enable bit in the system
+ * control register: */
+ if (arm_feature(env, ARM_FEATURE_SCTLR_TE_BIT)) {
env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
}
+
env->regs[14] = env->regs[15] + offset;
env->regs[15] = addr;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
--
1.9.1