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[Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function |
Date: |
Fri, 4 Sep 2015 16:05:46 +0100 |
From: Sergey Sorokin <address@hidden>
There is an error in arm_excp_unmasked() function:
bitwise operator & is used with integer and bool operands
causing an incorrect zeroed result.
The patch fixes it.
Signed-off-by: Sergey Sorokin <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c794afc..4bd5dc8 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1520,8 +1520,8 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
- uint32_t scr;
- uint32_t hcr;
+ bool scr;
+ bool hcr;
bool pstate_unmasked;
int8_t unmasked = 0;
@@ -1548,7 +1548,7 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
* set then FIQs can be masked by CPSR.F when non-secure but only
* when FIQs are only routed to EL3.
*/
- scr &= !((env->cp15.scr_el3 & SCR_FW) && !hcr);
+ scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
pstate_unmasked = !(env->daif & PSTATE_F);
break;
--
1.9.1
- [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]', Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 22/27] i.MX: Add SOC support for i.MX25, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 14/27] arm: Remove hw_error() usages., Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 19/27] i.MX: KZM: use standalone i.MX31 SOC support, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 15/27] target-arm: Fix AArch32:AArch64 general-purpose register mapping, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function,
Peter Maydell <=
- [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 25/27] i.MX: Add i2C devices to i.MX31 SOC, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 11/27] smbios: add smbios 3.0 support, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 13/27] arm: cpu: assert() on no-EL2 virt IRQ error condition., Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size, Peter Maydell, 2015/09/04