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[Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts |
Date: |
Tue, 8 Sep 2015 17:51:17 +0100 |
Although we were correctly handling interrupts becoming active
and then inactive, we weren't actually exposing this to the guest
by setting the 'active' flag for the interrupt, so reads
of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly
return zeroes. Correct this oversight.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/intc/arm_gic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 9daa8cd..2df550c 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -262,6 +262,7 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
}
s->running_priority[cpu] = prio;
+ GIC_SET_ACTIVE(irq, 1 << cpu);
}
static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
@@ -536,6 +537,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq,
MemTxAttrs attrs)
*/
gic_drop_prio(s, cpu, group);
+ GIC_CLEAR_ACTIVE(irq, cm);
gic_update(s);
}
--
1.9.1
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 19/20] xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 20/20] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 18/20] ahci.c: Don't assume AHCIState's parent is AHCIPCIState, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 16/20] cadence_gem: Correct Marvell PHY SPCFC reset value, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 14/20] target-arm: Correct opc1 for AT_S12Exx, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 13/20] target-arm: Log the target EL when taking exceptions, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC if we are using them, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts,
Peter Maydell <=
- [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 17/20] ahci: Separate the AHCI state structure into the header, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 10/20] hw/arm/virt: Default to not providing TrustZone support, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group priority, not full priority, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 03/20] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers, Peter Maydell, 2015/09/08