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[Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL |
Date: |
Mon, 14 Sep 2015 14:52:57 +0100 |
From: Richard Henderson <address@hidden>
These are all special case aliases of UBFM.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 8ae6814..f2f8443 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3038,6 +3038,23 @@ static void disas_bitfield(DisasContext *s, uint32_t
insn)
tcg_gen_sari_i64(tcg_rd, tcg_tmp, ri);
goto done;
}
+ } else if (opc == 2) { /* UBFM */
+ if (ri == 0) { /* UXTB, UXTH, plus non-canonical AND */
+ tcg_gen_andi_i64(tcg_rd, tcg_tmp, bitmask64(si + 1));
+ return;
+ }
+ if (si == 63 || (si == 31 && ri <= si)) { /* LSR */
+ if (si == 31) {
+ tcg_gen_ext32u_i64(tcg_tmp, tcg_tmp);
+ }
+ tcg_gen_shri_i64(tcg_rd, tcg_tmp, ri);
+ return;
+ }
+ if (si + 1 == ri && si != bitsize - 1) { /* LSL */
+ int shift = bitsize - 1 - si;
+ tcg_gen_shli_i64(tcg_rd, tcg_tmp, shift);
+ goto done;
+ }
}
if (opc != 1) { /* SBFM or UBFM */
--
1.9.1
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, (continued)
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 15/24] i.MX: Add GPIO devices to i.MX31 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 03/24] target-arm: Share all common TCG temporaries, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 14/24] i.MX: Add GPIO device, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL,
Peter Maydell <=
- [Qemu-devel] [PULL 16/24] i.MX: Add GPIO devices to i.MX25 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 04/24] target-arm: Introduce DisasCompare, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 02/24] xlnx-zynqmp: Remove unnecessary brackets around error messages, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 18/24] target-arm: Add VTCR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 09/24] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Peter Maydell, 2015/09/14
- Re: [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14