[Qemu-devel] [PATCH] target-tilegx: Implement v1multu instruction

[gang . chen . 5i5j]

From: Chen Gang <address@hidden>

Only according to v1add implementation.

Signed-off-by: Chen Gang <address@hidden>
---
 target-tilegx/helper.h      |  1 +
 target-tilegx/simd_helper.c | 13 +++++++++++++
 target-tilegx/translate.c   |  4 ++++
 3 files changed, 18 insertions(+)

diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index c366984..0af91af 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -6,6 +6,7 @@ DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
 DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
 
 DEF_HELPER_FLAGS_2(v1add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index ec589fe..d1cd9bc 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -192,3 +192,16 @@ uint64_t helper_v4shrs(uint64_t a, uint64_t b)
     }
     return r;
 }
+
+uint64_t helper_v1multu(uint64_t a, uint64_t b)
+{
+    uint64_t r = 0;
+    int i;
+
+    for (i = 0; i < 64; i += 8) {
+        uint64_t ae = (uint8_t)(a >> i);
+        uint64_t be = (uint8_t)(b >> i);
+        r |= ((ae * be) & 0xff) << i;
+    }
+    return r;
+}
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 2246243..4fc7cd7 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1074,7 +1074,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, 
unsigned opext,
     case OE_RRR(V1MINU, 0, X1):
     case OE_RRR(V1MNZ, 0, X0):
     case OE_RRR(V1MNZ, 0, X1):
+        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
     case OE_RRR(V1MULTU, 0, X0):
+        gen_helper_v1multu(tdest, tsrca, tsrcb);
+        mnemonic = "v1multu";
+        break;
     case OE_RRR(V1MULUS, 0, X0):
     case OE_RRR(V1MULU, 0, X0):
     case OE_RRR(V1MZ, 0, X0):
-- 
1.9.3