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[Qemu-devel] [PATCH v3] spapr: generate DT node names


From: Laurent Vivier
Subject: [Qemu-devel] [PATCH v3] spapr: generate DT node names
Date: Wed, 23 Sep 2015 14:14:03 +0200

When DT node names for PCI devices are generated by SLOF,
they are generated according to the type of the device
(for instance, ethernet for virtio-net-pci device).

Node name for hotplugged devices is generated by QEMU.
This patch adds the mechanic to QEMU to create the node
name according to the device type too.

The data structure has been roughly copied from OpenBIOS/OpenHackware,
node names from SLOF.

Example:

Hotplugging some PCI cards with QEMU monitor:

device_add virtio-tablet-pci
device_add virtio-serial-pci
device_add virtio-mouse-pci
device_add virtio-scsi-pci
device_add virtio-gpu-pci
device_add ne2k_pci
device_add nec-usb-xhci
device_add intel-hda

What we can see in linux device tree:

for dir in /proc/device-tree/address@hidden/address@hidden/; do
    echo $dir
    cat $dir/name
    echo
done

WITHOUT this patch:

/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci

WITH this patch:

/proc/device-tree/address@hidden/address@hidden/
communication-controller
/proc/device-tree/address@hidden/address@hidden/
display
/proc/device-tree/address@hidden/address@hidden/
ethernet
/proc/device-tree/address@hidden/address@hidden/
input-controller
/proc/device-tree/address@hidden/address@hidden/
mouse
/proc/device-tree/address@hidden/address@hidden/
multimedia-device
/proc/device-tree/address@hidden/address@hidden/
scsi
/proc/device-tree/address@hidden/address@hidden/
usb-xhci

Signed-off-by: Laurent Vivier <address@hidden>
---
v3: use values from pci_ids.h, update pci_ids.h values
    keep only details for USB (xhci, ohci, ...) and PIC (IO-APIC, IO-XAPIC)
v2: Use CamelCase name, remove misc-* name,
    remove _OTHER entries to fallback to class name (as SLOF does).
    Fix typo (IPMI-bltr).

 hw/ppc/spapr_pci.c       | 296 ++++++++++++++++++++++++++++++++++++++++++++---
 include/hw/pci/pci_ids.h | 115 ++++++++++++++++--
 2 files changed, 388 insertions(+), 23 deletions(-)

diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index a2feb4c..c521d31 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -38,6 +38,7 @@
 
 #include "hw/pci/pci_bridge.h"
 #include "hw/pci/pci_bus.h"
+#include "hw/pci/pci_ids.h"
 #include "hw/ppc/spapr_drc.h"
 #include "sysemu/device_tree.h"
 
@@ -944,6 +945,280 @@ static void populate_resource_props(PCIDevice *d, 
ResourceProps *rp)
     rp->assigned_len = assigned_idx * sizeof(ResourceFields);
 }
 
+typedef struct PCIClass PCIClass;
+typedef struct PCISubClass PCISubClass;
+typedef struct PCIIFace PCIIFace;
+
+struct PCIIFace {
+    uint8_t iface;
+    const char *name;
+};
+
+struct PCISubClass {
+    uint8_t subclass;
+    const char *name;
+    const PCIIFace *iface;
+};
+#define SUBCLASS(a) ((uint8_t)a)
+#define IFACE(a)    ((uint8_t)a)
+
+struct PCIClass {
+    const char *name;
+    const PCISubClass *subc;
+};
+
+static const PCISubClass undef_subclass[] = {
+    { IFACE(PCI_CLASS_NOT_DEFINED_VGA), "display", NULL },
+    { 0xFF, NULL, NULL, NULL },
+};
+
+static const PCISubClass mass_subclass[] = {
+    { SUBCLASS(PCI_CLASS_STORAGE_SCSI), "scsi", NULL },
+    { SUBCLASS(PCI_CLASS_STORAGE_IDE), "ide", NULL },
+    { SUBCLASS(PCI_CLASS_STORAGE_FLOPPY), "fdc", NULL },
+    { SUBCLASS(PCI_CLASS_STORAGE_IPI), "ipi", NULL },
+    { SUBCLASS(PCI_CLASS_STORAGE_RAID), "raid", NULL },
+    { SUBCLASS(PCI_CLASS_STORAGE_ATA), "ata", NULL },
+    { SUBCLASS(PCI_CLASS_STORAGE_SATA), "sata", NULL },
+    { SUBCLASS(PCI_CLASS_STORAGE_SAS), "sas", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass net_subclass[] = {
+    { SUBCLASS(PCI_CLASS_NETWORK_ETHERNET), "ethernet", NULL },
+    { SUBCLASS(PCI_CLASS_NETWORK_TOKEN_RING), "token-ring", NULL },
+    { SUBCLASS(PCI_CLASS_NETWORK_FDDI), "fddi", NULL },
+    { SUBCLASS(PCI_CLASS_NETWORK_ATM), "atm", NULL },
+    { SUBCLASS(PCI_CLASS_NETWORK_ISDN), "isdn", NULL },
+    { SUBCLASS(PCI_CLASS_NETWORK_WORDFIP), "worldfip", NULL },
+    { SUBCLASS(PCI_CLASS_NETWORK_PICMG214), "picmg", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass displ_subclass[] = {
+    { SUBCLASS(PCI_CLASS_DISPLAY_VGA), "vga", NULL },
+    { SUBCLASS(PCI_CLASS_DISPLAY_XGA), "xga", NULL },
+    { SUBCLASS(PCI_CLASS_DISPLAY_3D), "3d-controller", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass media_subclass[] = {
+    { SUBCLASS(PCI_CLASS_MULTIMEDIA_VIDEO), "video", NULL },
+    { SUBCLASS(PCI_CLASS_MULTIMEDIA_AUDIO), "sound", NULL },
+    { SUBCLASS(PCI_CLASS_MULTIMEDIA_PHONE), "telephony", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass mem_subclass[] = {
+    { SUBCLASS(PCI_CLASS_MEMORY_RAM), "memory", NULL },
+    { SUBCLASS(PCI_CLASS_MEMORY_FLASH), "flash", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+
+static const PCISubClass bridg_subclass[] = {
+    { SUBCLASS(PCI_CLASS_BRIDGE_HOST), "host", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_ISA), "isa", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_EISA), "eisa", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_MC), "mca", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_PCI), "pci", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_PCMCIA), "pcmcia", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_NUBUS), "nubus", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_CARDBUS), "cardbus", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_RACEWAY), "raceway", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_PCI_SEMITP), "semi-transparent-pci", NULL },
+    { SUBCLASS(PCI_CLASS_BRIDGE_IB_PCI), "infiniband", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass comm_subclass[] = {
+    { SUBCLASS(PCI_CLASS_COMMUNICATION_SERIAL), "serial", NULL },
+    { SUBCLASS(PCI_CLASS_COMMUNICATION_PARALLEL), "parallel", NULL },
+    { SUBCLASS(PCI_CLASS_COMMUNICATION_MULTISERIAL), "multiport-serial", NULL 
},
+    { SUBCLASS(PCI_CLASS_COMMUNICATION_MODEM), "modem", NULL },
+    { SUBCLASS(PCI_CLASS_COMMUNICATION_GPIB), "gpib", NULL },
+    { SUBCLASS(PCI_CLASS_COMMUNICATION_SC), "smart-card", NULL },
+    { 0xFF, NULL, NULL, NULL },
+};
+
+static const PCIIFace pic_iface[] = {
+    { IFACE(PCI_CLASS_SYSTEM_PIC_IOAPIC), "io-apic" },
+    { IFACE(PCI_CLASS_SYSTEM_PIC_IOXAPIC), "io-xapic" },
+    { 0xFF, NULL },
+};
+
+static const PCISubClass sys_subclass[] = {
+    { SUBCLASS(PCI_CLASS_SYSTEM_PIC), "interrupt-controller", pic_iface },
+    { SUBCLASS(PCI_CLASS_SYSTEM_DMA), "dma-controller", NULL },
+    { SUBCLASS(PCI_CLASS_SYSTEM_TIMER), "timer", NULL },
+    { SUBCLASS(PCI_CLASS_SYSTEM_RTC), "rtc", NULL },
+    { SUBCLASS(PCI_CLASS_SYSTEM_PCI_HOTPLUG), "hot-plug-controller", NULL },
+    { SUBCLASS(PCI_CLASS_SYSTEM_SDHCI), "sd-host-controller", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass inp_subclass[] = {
+    { SUBCLASS(PCI_CLASS_INPUT_KEYBOARD), "keyboard", NULL },
+    { SUBCLASS(PCI_CLASS_INPUT_PEN), "pen", NULL },
+    { SUBCLASS(PCI_CLASS_INPUT_MOUSE), "mouse", NULL },
+    { SUBCLASS(PCI_CLASS_INPUT_SCANNER), "scanner", NULL },
+    { SUBCLASS(PCI_CLASS_INPUT_GAMEPORT), "gameport", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass dock_subclass[] = {
+    { SUBCLASS(PCI_CLASS_DOCKING_GENERIC), "dock", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass cpu_subclass[] = {
+    { SUBCLASS(PCI_CLASS_PROCESSOR_386), "386", NULL },
+    { SUBCLASS(PCI_CLASS_PROCESSOR_486), "486", NULL },
+    { SUBCLASS(PCI_CLASS_PROCESSOR_PENTIUM), "pentium", NULL },
+    { SUBCLASS(PCI_CLASS_PROCESSOR_ALPHA), "alpha", NULL },
+    { SUBCLASS(PCI_CLASS_PROCESSOR_POWERPC), "powerpc", NULL },
+    { SUBCLASS(PCI_CLASS_PROCESSOR_MIPS), "mips", NULL },
+    { SUBCLASS(PCI_CLASS_PROCESSOR_CO), "co-processor", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCIIFace usb_iface[] = {
+    { IFACE(PCI_CLASS_SERIAL_USB_UHCI), "usb-uhci" },
+    { IFACE(PCI_CLASS_SERIAL_USB_OHCI), "usb-ohci", },
+    { IFACE(PCI_CLASS_SERIAL_USB_EHCI), "usb-ehci" },
+    { IFACE(PCI_CLASS_SERIAL_USB_XHCI), "usb-xhci" },
+    { IFACE(PCI_CLASS_SERIAL_USB_UNKNOWN), "usb-unknown" },
+    { IFACE(PCI_CLASS_SERIAL_USB_DEVICE), "usb-device" },
+    { 0xFF, NULL },
+};
+
+static const PCISubClass ser_subclass[] = {
+    { SUBCLASS(PCI_CLASS_SERIAL_FIREWIRE), "firewire", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_ACCESS), "access-bus", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_SSA), "ssa", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_USB), "usb", usb_iface },
+    { SUBCLASS(PCI_CLASS_SERIAL_FIBER), "fibre-channel", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_SMBUS), "smb", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_IB), "infiniband", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_IPMI), "ipmi", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_SERCOS), "sercos", NULL },
+    { SUBCLASS(PCI_CLASS_SERIAL_CANBUS), "canbus", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass wrl_subclass[] = {
+    { SUBCLASS(PCI_CLASS_WIRELESS_IRDA), "irda", NULL },
+    { SUBCLASS(PCI_CLASS_WIRELESS_CIR), "consumer-ir", NULL },
+    { SUBCLASS(PCI_CLASS_WIRELESS_RF_CONTROLLER), "rf-controller", NULL },
+    { SUBCLASS(PCI_CLASS_WIRELESS_BLUETOOTH), "bluetooth", NULL },
+    { SUBCLASS(PCI_CLASS_WIRELESS_BROADBAND), "broadband", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass sat_subclass[] = {
+    { SUBCLASS(PCI_CLASS_SATELLITE_TV), "satellite-tv", NULL },
+    { SUBCLASS(PCI_CLASS_SATELLITE_AUDIO), "satellite-audio", NULL },
+    { SUBCLASS(PCI_CLASS_SATELLITE_VOICE), "satellite-voice", NULL },
+    { SUBCLASS(PCI_CLASS_SATELLITE_DATA), "satellite-data", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass crypt_subclass[] = {
+    { SUBCLASS(PCI_CLASS_CRYPT_NETWORK), "network-encryption", NULL },
+    { SUBCLASS(PCI_CLASS_CRYPT_ENTERTAINMENT),
+      "entertainment-encryption", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCISubClass spc_subclass[] = {
+    { SUBCLASS(PCI_CLASS_SP_DPIO), "dpio", NULL },
+    { SUBCLASS(PCI_CLASS_SP_PERF), "counter", NULL },
+    { SUBCLASS(PCI_CLASS_SP_SYNCH), "measurement", NULL },
+    { SUBCLASS(PCI_CLASS_SP_MANAGEMENT), "management-card", NULL },
+    { 0xFF, NULL, NULL },
+};
+
+static const PCIClass pci_classes[] = {
+    { "unknown-legacy-device", undef_subclass },
+    { "mass-storage",  mass_subclass },
+    { "network", net_subclass },
+    { "display", displ_subclass, },
+    { "multimedia-device", media_subclass },
+    { "memory-controller", mem_subclass },
+    { "unknown-bridge", bridg_subclass },
+    { "communication-controller", comm_subclass},
+    { "system-peripheral", sys_subclass },
+    { "input-controller", inp_subclass },
+    { "docking-station", dock_subclass },
+    { "cpu", cpu_subclass },
+    { "serial-bus", ser_subclass },
+    { "wireless-controller", wrl_subclass },
+    { "intelligent-io", NULL },
+    { "satellite-device", sat_subclass },
+    { "encryption", crypt_subclass },
+    { "data-processing-controller", spc_subclass },
+};
+
+static const char *pci_find_device_name(uint8_t class, uint8_t subclass,
+                                        uint8_t iface)
+{
+    const PCIClass *pclass;
+    const PCISubClass *psubclass;
+    const PCIIFace *piface;
+    const char *name;
+
+    if (class > (sizeof(pci_classes) / sizeof(PCIClass))) {
+        return "pci";
+    }
+
+    pclass = pci_classes + class;
+    name = pclass->name;
+
+    if (pclass->subc == NULL) {
+        return name;
+    }
+
+    psubclass = pclass->subc;
+    while (psubclass->subclass != 0xff) {
+        if (psubclass->subclass == subclass) {
+            name = psubclass->name;
+            break;
+        }
+        psubclass++;
+    }
+
+    piface = psubclass->iface;
+    if (piface == NULL) {
+        return name;
+    }
+    while (piface->iface != 0xff) {
+        if (piface->iface == iface) {
+            name = piface->name;
+            break;
+        }
+        piface++;
+    }
+
+    return name;
+}
+
+static void pci_get_node_name(char *nodename, int len, PCIDevice *dev)
+{
+    int slot = PCI_SLOT(dev->devfn);
+    int func = PCI_FUNC(dev->devfn);
+    uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
+    const char *name;
+
+    name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
+                                ccode & 0xff);
+
+    if (func != 0) {
+        snprintf(nodename, len, "address@hidden,%x", name, slot, func);
+    } else {
+        snprintf(nodename, len, "address@hidden", name, slot);
+    }
+}
+
 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
                                             PCIDevice *pdev);
 
@@ -955,6 +1230,7 @@ static int spapr_populate_pci_child_dt(PCIDevice *dev, 
void *fdt, int offset,
     int pci_status, err;
     char *buf = NULL;
     uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev);
+    uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
 
     if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) ==
         PCI_HEADER_TYPE_BRIDGE) {
@@ -968,8 +1244,7 @@ static int spapr_populate_pci_child_dt(PCIDevice *dev, 
void *fdt, int offset,
                           pci_default_read_config(dev, PCI_DEVICE_ID, 2)));
     _FDT(fdt_setprop_cell(fdt, offset, "revision-id",
                           pci_default_read_config(dev, PCI_REVISION_ID, 1)));
-    _FDT(fdt_setprop_cell(fdt, offset, "class-code",
-                          pci_default_read_config(dev, PCI_CLASS_PROG, 3)));
+    _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
     if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) {
         _FDT(fdt_setprop_cell(fdt, offset, "interrupts",
                  pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)));
@@ -1010,11 +1285,10 @@ static int spapr_populate_pci_child_dt(PCIDevice *dev, 
void *fdt, int offset,
         _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
     }
 
-    /* NOTE: this is normally generated by firmware via path/unit name,
-     * but in our case we must set it manually since it does not get
-     * processed by OF beforehand
-     */
-    _FDT(fdt_setprop_string(fdt, offset, "name", "pci"));
+    _FDT(fdt_setprop_string(fdt, offset, "name",
+                            pci_find_device_name((ccode >> 16) & 0xff,
+                                                 (ccode >> 8) & 0xff,
+                                                 ccode & 0xff)));
     buf = spapr_phb_get_loc_code(sphb, dev);
     if (!buf) {
         error_report("Failed setting the ibm,loc-code");
@@ -1051,15 +1325,9 @@ static int spapr_create_pci_child_dt(sPAPRPHBState *phb, 
PCIDevice *dev,
                                      void *fdt, int node_offset)
 {
     int offset, ret;
-    int slot = PCI_SLOT(dev->devfn);
-    int func = PCI_FUNC(dev->devfn);
     char nodename[FDT_NAME_MAX];
 
-    if (func != 0) {
-        snprintf(nodename, FDT_NAME_MAX, "address@hidden,%x", slot, func);
-    } else {
-        snprintf(nodename, FDT_NAME_MAX, "address@hidden", slot);
-    }
+    pci_get_node_name(nodename, FDT_NAME_MAX, dev);
     offset = fdt_add_subnode(fdt, node_offset, nodename);
     ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb);
 
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index d98e6c9..42c86df 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -12,41 +12,84 @@
 
 /* Device classes and subclasses */
 
-#define PCI_BASE_CLASS_STORAGE           0x01
-#define PCI_BASE_CLASS_NETWORK           0x02
+#define PCI_CLASS_NOT_DEFINED            0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA        0x0001
 
+#define PCI_BASE_CLASS_STORAGE           0x01
 #define PCI_CLASS_STORAGE_SCSI           0x0100
 #define PCI_CLASS_STORAGE_IDE            0x0101
+#define PCI_CLASS_STORAGE_FLOPPY         0x0102
+#define PCI_CLASS_STORAGE_IPI            0x0103
 #define PCI_CLASS_STORAGE_RAID           0x0104
+#define PCI_CLASS_STORAGE_ATA            0x0105
 #define PCI_CLASS_STORAGE_SATA           0x0106
+#define PCI_CLASS_STORAGE_SAS            0x0107
 #define PCI_CLASS_STORAGE_EXPRESS        0x0108
 #define PCI_CLASS_STORAGE_OTHER          0x0180
 
+#define PCI_BASE_CLASS_NETWORK           0x02
 #define PCI_CLASS_NETWORK_ETHERNET       0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING     0x0201
+#define PCI_CLASS_NETWORK_FDDI           0x0202
+#define PCI_CLASS_NETWORK_ATM            0x0203
+#define PCI_CLASS_NETWORK_ISDN           0x0204
+#define PCI_CLASS_NETWORK_WORDFIP        0x0205
+#define PCI_CLASS_NETWORK_PICMG214       0x0206
 #define PCI_CLASS_NETWORK_OTHER          0x0280
 
+#define PCI_BASE_CLASS_DISPLAY           0x03
 #define PCI_CLASS_DISPLAY_VGA            0x0300
+#define PCI_CLASS_DISPLAY_XGA            0x0301
+#define PCI_CLASS_DISPLAY_3D             0x0302
 #define PCI_CLASS_DISPLAY_OTHER          0x0380
 
+#define PCI_BASE_CLASS_MULTIMEDIA        0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO       0x0400
 #define PCI_CLASS_MULTIMEDIA_AUDIO       0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE       0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER       0x0480
 
+#define PCI_BASE_CLASS_MEMORY            0x05
 #define PCI_CLASS_MEMORY_RAM             0x0500
+#define PCI_CLASS_MEMORY_FLASH           0x0501
+#define PCI_CLASS_MEMORY_OTHER           0x0580
 
-#define PCI_CLASS_SYSTEM_SDHCI           0x0805
-#define PCI_CLASS_SYSTEM_OTHER           0x0880
-
-#define PCI_CLASS_SERIAL_USB             0x0c03
-#define PCI_CLASS_SERIAL_SMBUS           0x0c05
-
+#define PCI_BASE_CLASS_BRIDGE            0x06
 #define PCI_CLASS_BRIDGE_HOST            0x0600
 #define PCI_CLASS_BRIDGE_ISA             0x0601
+#define PCI_CLASS_BRIDGE_EISA            0x0602
+#define PCI_CLASS_BRIDGE_MC              0x0603
 #define PCI_CLASS_BRIDGE_PCI             0x0604
 #define PCI_CLASS_BRIDGE_PCI_INF_SUB     0x01
+#define PCI_CLASS_BRIDGE_PCMCIA          0x0605
+#define PCI_CLASS_BRIDGE_NUBUS           0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS         0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY         0x0608
+#define PCI_CLASS_BRIDGE_PCI_SEMITP      0x0609
+#define PCI_CLASS_BRIDGE_IB_PCI          0x060a
 #define PCI_CLASS_BRIDGE_OTHER           0x0680
 
+#define PCI_BASE_CLASS_COMMUNICATION     0x07
 #define PCI_CLASS_COMMUNICATION_SERIAL   0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM    0x0703
+#define PCI_CLASS_COMMUNICATION_GPIB     0x0704
+#define PCI_CLASS_COMMUNICATION_SC       0x0705
 #define PCI_CLASS_COMMUNICATION_OTHER    0x0780
 
+#define PCI_BASE_CLASS_SYSTEM            0x08
+#define PCI_CLASS_SYSTEM_PIC             0x0800
+#define PCI_CLASS_SYSTEM_PIC_IOAPIC      0x080010
+#define PCI_CLASS_SYSTEM_PIC_IOXAPIC     0x080020
+#define PCI_CLASS_SYSTEM_DMA             0x0801
+#define PCI_CLASS_SYSTEM_TIMER           0x0802
+#define PCI_CLASS_SYSTEM_RTC             0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG     0x0804
+#define PCI_CLASS_SYSTEM_SDHCI           0x0805
+#define PCI_CLASS_SYSTEM_OTHER           0x0880
+
+#define PCI_BASE_CLASS_INPUT             0x09
 #define PCI_CLASS_INPUT_KEYBOARD         0x0900
 #define PCI_CLASS_INPUT_PEN              0x0901
 #define PCI_CLASS_INPUT_MOUSE            0x0902
@@ -54,8 +97,62 @@
 #define PCI_CLASS_INPUT_GAMEPORT         0x0904
 #define PCI_CLASS_INPUT_OTHER            0x0980
 
-#define PCI_CLASS_PROCESSOR_CO           0x0b40
+#define PCI_BASE_CLASS_DOCKING           0x0a
+#define PCI_CLASS_DOCKING_GENERIC        0x0a00
+#define PCI_CLASS_DOCKING_OTHER          0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR         0x0b
+#define PCI_CLASS_PROCESSOR_386          0x0b00
+#define PCI_CLASS_PROCESSOR_486          0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM      0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA        0x0b10
 #define PCI_CLASS_PROCESSOR_POWERPC      0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS         0x0b30
+#define PCI_CLASS_PROCESSOR_CO           0x0b40
+
+#define PCI_BASE_CLASS_SERIAL            0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE        0x0c00
+#define PCI_CLASS_SERIAL_ACCESS          0x0c01
+#define PCI_CLASS_SERIAL_SSA             0x0c02
+#define PCI_CLASS_SERIAL_USB             0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI        0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI        0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI        0x0c0320
+#define PCI_CLASS_SERIAL_USB_XHCI        0x0c0330
+#define PCI_CLASS_SERIAL_USB_UNKNOWN     0x0c0380
+#define PCI_CLASS_SERIAL_USB_DEVICE      0x0c03fe
+#define PCI_CLASS_SERIAL_FIBER           0x0c04
+#define PCI_CLASS_SERIAL_SMBUS           0x0c05
+#define PCI_CLASS_SERIAL_IB              0x0c06
+#define PCI_CLASS_SERIAL_IPMI            0x0c07
+#define PCI_CLASS_SERIAL_SERCOS          0x0c08
+#define PCI_CLASS_SERIAL_CANBUS          0x0c09
+
+#define PCI_BASE_CLASS_WIRELESS          0x0d
+#define PCI_CLASS_WIRELESS_IRDA          0x0d00
+#define PCI_CLASS_WIRELESS_CIR           0x0d01
+#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10
+#define PCI_CLASS_WIRELESS_BLUETOOTH     0x0d11
+#define PCI_CLASS_WIRELESS_BROADBAND     0x0d12
+#define PCI_CLASS_WIRELESS_OTHER         0x0d80
+
+#define PCI_BASE_CLASS_SATELLITE         0x0f
+#define PCI_CLASS_SATELLITE_TV           0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO        0x0f01
+#define PCI_CLASS_SATELLITE_VOICE        0x0f03
+#define PCI_CLASS_SATELLITE_DATA         0x0f04
+
+#define PCI_BASE_CLASS_CRYPT             0x10
+#define PCI_CLASS_CRYPT_NETWORK          0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT    0x1001
+#define PCI_CLASS_CRYPT_OTHER            0x1080
+
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define PCI_CLASS_SP_DPIO                0x1100
+#define PCI_CLASS_SP_PERF                0x1101
+#define PCI_CLASS_SP_SYNCH               0x1110
+#define PCI_CLASS_SP_MANAGEMENT          0x1120
+#define PCI_CLASS_SP_OTHER               0x1180
 
 #define PCI_CLASS_OTHERS                 0xff
 
-- 
2.4.3




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