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[Qemu-devel] [PATCH] target-tilegx: Check zero dest register for ld inst
From: |
gang . chen . 5i5j |
Subject: |
[Qemu-devel] [PATCH] target-tilegx: Check zero dest register for ld instructions |
Date: |
Mon, 28 Sep 2015 21:51:27 +0800 |
From: Chen Gang <address@hidden>
At present, qemu x86_64 host backend can not remove the related dummy
instructions. Even the worse, sometimes, it will generate the incorrect
instructions which will cause segment fault for prefetch_l3 instruction.
Signed-off-by: Chen Gang <address@hidden>
---
target-tilegx/translate.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 86da6b5..7232361 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -620,7 +620,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
memop = MO_TEQ;
mnemonic = "ld";
do_load:
- tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ if (dest != TILEGX_R_ZERO) {
+ tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ }
break;
case OE_RR_X1(LDNA):
tcg_gen_andi_tl(tdest, tsrca, ~7);
@@ -1987,8 +1989,10 @@ static TileExcp decode_y2(DisasContext *dc,
tilegx_bundle_bits bundle)
memop = MO_TEQ;
mnemonic = "ld";
do_load:
- tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
- dc->mmuidx, memop);
+ if (srcbdest != TILEGX_R_ZERO) {
+ tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
+ dc->mmuidx, memop);
+ }
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
reg_names[srcbdest], reg_names[srca]);
return TILEGX_EXCP_NONE;
--
1.9.3
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