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[Qemu-devel] [PULL 04/19] target-tilegx: Implement v1multu instruction
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 04/19] target-tilegx: Implement v1multu instruction |
Date: |
Wed, 7 Oct 2015 20:33:02 +1100 |
From: Chen Gang <address@hidden>
Signed-off-by: Chen Gang <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/helper.h | 1 +
target-tilegx/simd_helper.c | 13 +++++++++++++
target-tilegx/translate.c | 4 ++++
3 files changed, 18 insertions(+)
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index b253722..d380d3b 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -5,6 +5,7 @@ DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index 1c59a92..2cff43c 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -28,6 +28,19 @@
#define V2(X) (((X) & 0xffff) * 0x0001000100010001ull)
+uint64_t helper_v1multu(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 8) {
+ unsigned ae = extract64(a, i, 8);
+ unsigned be = extract64(b, i, 8);
+ r = deposit64(r, i, 8, ae * be);
+ }
+ return r;
+}
+
uint64_t helper_v1shl(uint64_t a, uint64_t b)
{
uint64_t m;
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 14ebd07..6bfb1af 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1155,7 +1155,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
case OE_RRR(V1MINU, 0, X1):
case OE_RRR(V1MNZ, 0, X0):
case OE_RRR(V1MNZ, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1MULTU, 0, X0):
+ gen_helper_v1multu(tdest, tsrca, tsrcb);
+ mnemonic = "v1multu";
+ break;
case OE_RRR(V1MULUS, 0, X0):
case OE_RRR(V1MULU, 0, X0):
case OE_RRR(V1MZ, 0, X0):
--
2.4.3
- [Qemu-devel] [PULL 00/19] Collected tilegx patches, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 02/19] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 04/19] target-tilegx: Implement v1multu instruction,
Richard Henderson <=
- [Qemu-devel] [PULL 19/19] target-tilegx: Support iret instruction and related special registers, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 07/19] target-tilegx: Implement complex multiply instructions, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 14/19] target-tilegx: Handle nofault prefetch instructions, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 08/19] target-tilegx: Let x1 pipe process bpt instruction only, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 09/19] linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 12/19] target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 01/19] target-tilegx: Tidy simd_helper.c, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 06/19] target-tilegx: Implement table index instructions, Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 13/19] target-tilegx: Fix a typo for mnemonic about "ld_add", Richard Henderson, 2015/10/08
- [Qemu-devel] [PULL 15/19] target-tilegx: Implement v2sh* instructions, Richard Henderson, 2015/10/08