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[Qemu-devel] [PATCH v4 07/13] target-arm: Add support for S2 page-table
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v4 07/13] target-arm: Add support for S2 page-table protection bits |
Date: |
Thu, 15 Oct 2015 00:55:40 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 41 +++++++++++++++++++++++++++++++++++++----
1 file changed, 37 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8530f7e..d1ffcdf 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6015,6 +6015,28 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx
mmu_idx, int ap)
return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
}
+/* Translate S2 section/page access permissions to protection flags
+ *
+ * @env: CPUARMState
+ * @s2ap: The 2-bit stage2 access permissions (S2AP)
+ * @xn: XN (execute-never) bit
+ */
+static int get_S2prot(CPUARMState *env, int s2ap, int xn)
+{
+ int prot = 0;
+
+ if (s2ap & 1) {
+ prot |= PAGE_READ;
+ }
+ if (s2ap & 2) {
+ prot |= PAGE_WRITE;
+ }
+ if (!xn) {
+ prot |= PAGE_EXEC;
+ }
+ return prot;
+}
+
/* Translate section/page access permissions to protection flags
*
* @env: CPUARMState
@@ -6715,9 +6737,15 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
*/
page_size = (1ULL << ((stride * (4 - level)) + 3));
descaddr |= (address & (page_size - 1));
- /* Extract attributes from the descriptor and merge with table attrs */
+ /* Extract attributes from the descriptor */
attrs = extract64(descriptor, 2, 10)
| (extract64(descriptor, 52, 12) << 10);
+
+ if (mmu_idx == ARMMMUIdx_S2NS) {
+ /* Stage 2 table descriptors do not include any attribute fields */
+ break;
+ }
+ /* Merge in attributes from table descriptors */
attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
@@ -6739,11 +6767,16 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
}
ap = extract32(attrs, 4, 2);
- ns = extract32(attrs, 3, 1);
xn = extract32(attrs, 12, 1);
- pxn = extract32(attrs, 11, 1);
- *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
+ if (mmu_idx == ARMMMUIdx_S2NS) {
+ ns = true;
+ *prot = get_S2prot(env, ap, xn);
+ } else {
+ ns = extract32(attrs, 3, 1);
+ pxn = extract32(attrs, 11, 1);
+ *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
+ }
fault_type = permission_fault;
if (!(*prot & (1 << access_type))) {
--
1.9.1
- Re: [Qemu-devel] [PATCH v4 04/13] target-arm: lpae: Replace tsz with computed inputsize, (continued)
- [Qemu-devel] [PATCH v4 11/13] target-arm: Add S2 translation to 32bit S1 PTWs, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 12/13] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 09/13] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 10/13] target-arm: Add S2 translation to 64bit S1 PTWs, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 07/13] target-arm: Add support for S2 page-table protection bits,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v4 08/13] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 13/13] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 05/13] target-arm: lpae: Rename granule_sz to stride, Edgar E. Iglesias, 2015/10/15
- [Qemu-devel] [PATCH v4 06/13] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/10/15