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[Qemu-devel] [PULL 02/13] target-i386: Disable cache info passthrough by
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 02/13] target-i386: Disable cache info passthrough by default |
Date: |
Fri, 23 Oct 2015 13:33:01 -0200 |
The host cache information may not make sense for the guest if the VM
CPU topology doesn't match the host CPU topology. To make sure we won't
expose broken cache information to the guest, disable cache info
passthrough by default, and add a new "host-cache-info" property that
can be used to enable the old behavior for users that really need it.
Cc: BenoƮt Canet <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
include/hw/i386/pc.h | 5 +++++
target-i386/cpu.c | 4 +---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c5961d7..7037de0 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -318,6 +318,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = "Broadwell-noTSX-" TYPE_X86_CPU,\
.property = "abm",\
.value = "off",\
+ },\
+ {\
+ .driver = "host" "-" TYPE_X86_CPU,\
+ .property = "host-cache-info",\
+ .value = "on",\
},
#define PC_COMPAT_2_3 \
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 5f53af2..987253d 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -656,7 +656,6 @@ struct X86CPUDefinition {
int stepping;
FeatureWordArray features;
char model_id[48];
- bool cache_info_passthrough;
};
static X86CPUDefinition builtin_x86_defs[] = {
@@ -1420,6 +1419,7 @@ static X86CPUDefinition host_cpudef;
static Property host_x86_cpu_properties[] = {
DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
+ DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
DEFINE_PROP_END_OF_LIST()
};
@@ -1446,7 +1446,6 @@ static void host_x86_cpu_class_init(ObjectClass *oc, void
*data)
cpu_x86_fill_model_id(host_cpudef.model_id);
xcc->cpu_def = &host_cpudef;
- host_cpudef.cache_info_passthrough = true;
/* level, xlevel, xlevel2, and the feature words are initialized on
* instance_init, because they require KVM to be initialized.
@@ -2094,7 +2093,6 @@ static void x86_cpu_load_def(X86CPU *cpu,
X86CPUDefinition *def, Error **errp)
object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
- cpu->cache_info_passthrough = def->cache_info_passthrough;
object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
for (w = 0; w < FEATURE_WORDS; w++) {
env->features[w] = def->features[w];
--
2.1.0
- [Qemu-devel] [PULL 00/13] X86 queue, 2015-10-23, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 02/13] target-i386: Disable cache info passthrough by default,
Eduardo Habkost <=
- [Qemu-devel] [PULL 01/13] target-i386: allow any alignment for SMBASE, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 03/13] target-i386: Introduce cpu_x86_update_dr7, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 04/13] target-i386: Re-introduce optimal breakpoint removal, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 05/13] target-i386: Ensure bit 10 on DR7 is never cleared, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 07/13] target-i386: Optimize setting dr[0-3], Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 06/13] target-i386: Move hw_*breakpoint_* functions, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 08/13] target-i386: Handle I/O breakpoints, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 10/13] target-i386: Ensure always-1 bits on DR6 can't be cleared, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 09/13] target-i386: Check CR4[DE] for processing DR4/DR5, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 11/13] target-i386: Add DE to TCG_FEATURES, Eduardo Habkost, 2015/10/23