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[Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-en
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-enabled interrupts in R6 |
Date: |
Fri, 30 Oct 2015 15:00:45 +0000 |
In Release 6, the behaviour of WAIT has been modified to make it a
requirement that a processor that has disabled operation as a result of
executing a WAIT will resume operation on arrival of an interrupt even if
interrupts are not enabled.
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/cpu.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index bbfee45..639a24b 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -53,12 +53,13 @@ static bool mips_cpu_has_work(CPUState *cs)
CPUMIPSState *env = &cpu->env;
bool has_work = false;
- /* It is implementation dependent if non-enabled interrupts
- wake-up the CPU, however most of the implementations only
+ /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
+ interrupts wake-up the CPU, however most of the implementations only
check for interrupts that can be taken. */
if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
- if (cpu_mips_hw_interrupts_enabled(env)) {
+ if (cpu_mips_hw_interrupts_enabled(env) ||
+ (env->insn_flags & ISA_MIPS32R6)) {
has_work = true;
}
}
--
2.1.0
- [Qemu-devel] [PULL 0/9] target-mips queue, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 1/9] target-mips: move the test for enabled interrupts to a separate function, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 5/9] hw/mips_malta: Fix KVM PC initialisation, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 9/9] target-mips: fix updating XContext on mmu exception, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-enabled interrupts in R6,
Leon Alrae <=
- [Qemu-devel] [PULL 6/9] target-mips: add PC, XNP reg numbers to RDHWR, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 4/9] target-mips: Add enum for BREAK32, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 7/9] target-mips: Set Config5.XNP for R6 cores, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction, Leon Alrae, 2015/10/30
- Re: [Qemu-devel] [PULL 0/9] target-mips queue, Peter Maydell, 2015/10/30