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[Qemu-devel] [PULL 10/13] target-arm: Report S/NS status in the CPU debu
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/13] target-arm: Report S/NS status in the CPU debug logs |
Date: |
Tue, 3 Nov 2015 14:13:16 +0000 |
If this CPU supports EL3, enhance the printing of the current
CPU mode in debug logging to distinguish S from NS modes as
appropriate.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
---
target-arm/translate-a64.c | 11 ++++++++++-
target-arm/translate.c | 12 +++++++++++-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 57503a0..d7e0954 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -127,6 +127,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
uint32_t psr = pstate_read(env);
int i;
int el = arm_current_el(env);
+ const char *ns_status;
cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
env->pc, env->xregs[31]);
@@ -138,12 +139,20 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, " ");
}
}
- cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n",
+
+ if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
+ } else {
+ ns_status = "";
+ }
+
+ cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
psr,
psr & PSTATE_N ? 'N' : '-',
psr & PSTATE_Z ? 'Z' : '-',
psr & PSTATE_C ? 'C' : '-',
psr & PSTATE_V ? 'V' : '-',
+ ns_status,
el,
psr & PSTATE_SP ? 'h' : 't');
diff --git a/target-arm/translate.c b/target-arm/translate.c
index b10a455..ff262a2 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11602,6 +11602,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
CPUARMState *env = &cpu->env;
int i;
uint32_t psr;
+ const char *ns_status;
if (is_a64(env)) {
aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
@@ -11616,13 +11617,22 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
cpu_fprintf(f, " ");
}
psr = cpsr_read(env);
- cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
+
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
+ (psr & CPSR_M) != ARM_CPU_MODE_MON) {
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
+ } else {
+ ns_status = "";
+ }
+
+ cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
psr,
psr & (1 << 31) ? 'N' : '-',
psr & (1 << 30) ? 'Z' : '-',
psr & (1 << 29) ? 'C' : '-',
psr & (1 << 28) ? 'V' : '-',
psr & CPSR_T ? 'T' : 'A',
+ ns_status,
cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
if (flags & CPU_DUMP_FPU) {
--
1.9.1
- [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 11/13] hw/arm/virt-acpi-build: _CCA attribute is compulsory, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 09/13] target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 04/13] arm: xilinx_zynq: Add linux pre-boot, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 10/13] target-arm: Report S/NS status in the CPU debug logs,
Peter Maydell <=
- [Qemu-devel] [PULL 07/13] arm: stellaris: exit on external reset request, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 13/13] ARM: ACPI: Fix MPIDR value in ACPI table, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 03/13] arm: boot: Add board specific setup code API, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 08/13] MAINTAINERS: Add new qemu-arm mailing list to ARM related entries, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 05/13] armv7-m: Return DeviceState* from armv7m_init(), Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 12/13] hw/arm/virt-acpi-build: Add GICC ACPI subtable for GICv3, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 02/13] arm: boot: Adjust indentation of FIXUP comments, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 01/13] target-arm: Add and use symbolic names for register banks, Peter Maydell, 2015/11/03
- [Qemu-devel] [PULL 06/13] armv7-m: Implement SYSRESETREQ, Peter Maydell, 2015/11/03
- Re: [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2015/11/03