[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH V2 0/3] target-i386: add memory protection-key suppo
From: |
Huaitong Han |
Subject: |
[Qemu-devel] [PATCH V2 0/3] target-i386: add memory protection-key support |
Date: |
Mon, 16 Nov 2015 15:52:34 +0800 |
Changes in v2:
*Fix memcpy error for xsave state.
*Fix TCG_7_0_ECX_FEATURES to 0.
*Make subjects more readable.
The protection-key feature provides an additional mechanism by which IA-32e
paging controls access to usermode addresses.
Hardware support for protection keys for user pages is enumerated with CPUID
feature flag CPUID.7.0.ECX[3]:PKU. Software support is CPUID.7.0.ECX[4]:OSPKE
with the setting of CR4.PKE(bit 22).
The PKRU register is XSAVE-managed state CPUID.D.0.EAX[9], the size of XSAVE
state component for PKRU is 8 bytes, the offset is 0xa80.
The specification of Protection Keys can be found at SDM (4.6.2, volume 3)
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
Huaitong Han (3):
target-i386: add pkeys support for cpuid handling
target-i386: add pkeys support for xsave state handling
target-i386: add pkeys support for vm migration
target-i386/cpu.c | 23 ++++++++++++++++++++++-
target-i386/cpu.h | 7 +++++++
target-i386/kvm.c | 3 +++
target-i386/machine.c | 23 +++++++++++++++++++++++
4 files changed, 55 insertions(+), 1 deletion(-)
--
2.4.3
- [Qemu-devel] [PATCH V2 0/3] target-i386: add memory protection-key support,
Huaitong Han <=