Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU

[Kevin O'Connor]

On Thu, Jan 14, 2016 at 07:29:40PM +0300, David kiarie wrote:
> On Thu, Jan 14, 2016 at 7:19 PM, Jan Kiszka <address@hidden> wrote:
> > On 2016-01-14 17:09, David kiarie wrote:
> >> On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka <address@hidden> wrote:
> >>> On 2016-01-14 16:39, Michael S. Tsirkin wrote:
> >>>> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote:
> >>>>> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin <address@hidden> 
> >>>>> wrote:
> >>>>>> then the way that works seems to be by guest
> >>>>>> programming the MMIO base.
> >>>>>> We should do the same: patch seabios and EFI to do this.
> >>>>>
> >>>>> Yes, that's the spec.
> >>>>>
> >>>>> We thought this could be possible via ACPI (without patching BIOS ), no 
> >>>>> ?
> >>>>
> >>>> I don't see how. We should do it the way it happens on real hardware.
> >>>>
> >>>
> >>> Doesn't Seabios retrieve certain ACPI fragments from QEMU via a
> >>> pv-interface by now?
> >>>
> >>> Anyway, the question remains where this address comes from: The BIOS,
> >>> which then writes it into some hw config register and reports it in
> >>> addition via ACPI or the hardware (hard-wired).
> >>
> >> Will look at patching BIOS.
> >
> > Scanning through the spec again: As the address is not hard-wired but
> > configured via registers in the extended capabilities of the
> > corresponding PCI functions of an IOMMU (and also enabled that way!),
> > it's up to the BIOS to allocate an appropriate address for a system.
> 
> Is there a way to modify IVRS/ACPI table from seabios because the same
> address is supposed to be the IVRS table otherwise I'd have to
> hard-code it :/

There are generally two ways to do this - have QEMU set the addresses
(in ACPI and/or fwcfg) and then SeaBIOS honors those addresses when
programming the hardware - or SeaBIOS programs the addresses before
reading the ACPI tables from fwcfg and then QEMU builds the tables
with the addresses that were programmed into hardware when the tables
are read from fwcfg.

As with my previous email, how does a typical factory BIOS determine
what to program to these registers?  Is it hardcoded or allocated from
a range in some way?

-Kevin