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[Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return event checks |
Date: |
Thu, 21 Jan 2016 14:56:27 +0000 |
We already implement almost all the checks for the illegal
return events from AArch64 state described in the ARM ARM section
D1.11.2. Add the two missing ones:
* return to EL2 when EL3 is implemented and SCR_EL3.NS is 0
* return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1
(We don't implement external debug, so the case of "debug state exit
from EL0 using AArch64 state to EL0 using AArch32 state" doesn't apply
for QEMU.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
target-arm/op_helper.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index b9f51e0..40224a8 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -719,6 +719,16 @@ void HELPER(exception_return)(CPUARMState *env)
goto illegal_return;
}
+ if (new_el == 2 && arm_is_secure_below_el3(env)) {
+ /* Return to the non-existent secure-EL2 */
+ goto illegal_return;
+ }
+
+ if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE)
+ && !arm_is_secure_below_el3(env)) {
+ goto illegal_return;
+ }
+
if (!return_to_aa64) {
env->aarch64 = 0;
env->uncached_cpsr = spsr & CPSR_M;
--
1.9.1
- [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init, (continued)
- [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 14/36] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 21/36] target-arm: Implement asidx_from_attrs, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 01/36] qdev: get_child_bus(): Use QOM lookup if available, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 19/36] qom/cpu: Add MemoryRegion property, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 25/36] hw/arm/virt: add secure memory region and UART, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return event checks,
Peter Maydell <=
- [Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 07/36] misc: zynq-xadc: Fix off-by-one, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 11/36] cpu: Add new get_phys_page_attrs_debug() method, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 15/36] exec.c: Add cpu_get_address_space(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 04/36] xilinx_spips: Separate the state struct into a header, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 09/36] exec.c: Allow target CPUs to define multiple AddressSpaces, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 02/36] m25p80.c: Add sst25wf080 SPI flash device, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 22/36] target-arm: Implement cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 17/36] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 13/36] cputlb.c: Use correct address space when looking up MemoryRegionSection, Peter Maydell, 2016/01/21