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Re: [Qemu-devel] [PATCH v4 6/8] bcm2836: add bcm2836 soc device
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v4 6/8] bcm2836: add bcm2836 soc device |
Date: |
Thu, 28 Jan 2016 20:50:26 -0800 |
SoC in subject line.
On Fri, Jan 15, 2016 at 3:58 PM, Andrew Baumann
<address@hidden> wrote:
> This is the SoC for Raspberry Pi 2.
>
> Signed-off-by: Andrew Baumann <address@hidden>
> ---
>
> Notes:
> v4:
> * s/ic/control/
> * replace use of smp_cpus with enabled-cpus property
> * propagate errors rather than exit(1)
>
> hw/arm/Makefile.objs | 2 +-
> hw/arm/bcm2836.c | 165
> +++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/bcm2836.h | 34 ++++++++++
> 3 files changed, 200 insertions(+), 1 deletion(-)
> create mode 100644 hw/arm/bcm2836.c
> create mode 100644 include/hw/arm/bcm2836.h
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 82cc142..f55f8d2 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -11,7 +11,7 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o
> pxa2xx_pic.o
> obj-$(CONFIG_DIGIC) += digic.o
> obj-y += omap1.o omap2.o strongarm.o
> obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
> -obj-$(CONFIG_RASPI) += bcm2835_peripherals.o
> +obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o
> obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
> obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
> obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
> new file mode 100644
> index 0000000..0fd6118
> --- /dev/null
> +++ b/hw/arm/bcm2836.c
> @@ -0,0 +1,165 @@
> +/*
> + * Raspberry Pi emulation (c) 2012 Gregory Estrade
> + * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
> + *
> + * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
> + * Written by Andrew Baumann
> + *
> + * This code is licensed under the GNU GPLv2 and later.
> + */
> +
> +#include "hw/arm/bcm2836.h"
> +#include "hw/arm/raspi_platform.h"
> +#include "hw/sysbus.h"
> +#include "exec/address-spaces.h"
> +
> +/* Peripheral base address seen by the CPU */
> +#define BCM2836_PERI_BASE 0x3F000000
> +
> +/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
> +#define BCM2836_CONTROL_BASE 0x40000000
> +
> +static void bcm2836_init(Object *obj)
> +{
> + BCM2836State *s = BCM2836(obj);
> + int n;
> +
> + for (n = 0; n < BCM2836_NCPUS; n++) {
> + object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
> + "cortex-a15-" TYPE_ARM_CPU);
> + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
> + &error_abort);
> + }
> +
> + object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
> + object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
> + qdev_set_parent_bus(DEVICE(&s->control), sysbus_get_default());
> +
> + object_initialize(&s->peripherals, sizeof(s->peripherals),
> + TYPE_BCM2835_PERIPHERALS);
> + object_property_add_child(obj, "peripherals", OBJECT(&s->peripherals),
> + &error_abort);
> + qdev_set_parent_bus(DEVICE(&s->peripherals), sysbus_get_default());
> +}
> +
> +static void bcm2836_realize(DeviceState *dev, Error **errp)
> +{
> + BCM2836State *s = BCM2836(dev);
> + Object *obj;
> + Error *err = NULL;
> + int n;
> +
> + /* common peripherals from bcm2835 */
> +
> + obj = object_property_get_link(OBJECT(dev), "ram", &err);
> + if (obj == NULL) {
> + error_setg(errp, "%s: required ram link not found: %s",
> + __func__, error_get_pretty(err));
> + return;
> + }
> +
> + object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj,
> &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + object_property_set_bool(OBJECT(&s->peripherals), true, "realized",
> &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
> + BCM2836_PERI_BASE, 1);
> +
> + /* bcm2836 interrupt controller (and mailboxes, etc.) */
> + object_property_set_bool(OBJECT(&s->control), true, "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, BCM2836_CONTROL_BASE);
> +
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
> + qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
> + qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
> +
> + for (n = 0; n < BCM2836_NCPUS; n++) {
> + /* Mirror bcm2836, which has clusterid set to 0xf
> + * TODO: this should be converted to a property of ARM_CPU
> + */
> + s->cpus[n].mp_affinity = 0xF00 | n;
> +
> + /* set periphbase/CBAR value for CPU-local registers */
> + object_property_set_int(OBJECT(&s->cpus[n]),
> + BCM2836_PERI_BASE + MCORE_OFFSET,
> + "reset-cbar", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + /* start powered off if not enabled */
> + object_property_set_bool(OBJECT(&s->cpus[n]), n >= s->enabled_cpus,
> + "start-powered-off", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + object_property_set_bool(OBJECT(&s->cpus[n]), true, "realized",
> &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + /* Connect irq/fiq outputs from the interrupt controller. */
> + qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
> + qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_IRQ));
> + qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
> + qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_FIQ));
> +
> + /* Connect timers from the CPU to the interrupt controller */
> + s->cpus[n].gt_timer_outputs[GTIMER_PHYS]
> + = qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", 0);
> + s->cpus[n].gt_timer_outputs[GTIMER_VIRT]
> + = qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", 0);
ARM CPU has
qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
ARRAY_SIZE(cpu->gt_timer_outputs));
So you should be able to use qdev_connect_gpio_out rather than direct
assignment.
> + }
> +}
> +
> +static Property bcm2836_props[] = {
> + DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus,
> BCM2836_NCPUS),
> + DEFINE_PROP_END_OF_LIST()
> +};
> +
> +static void bcm2836_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->props = bcm2836_props;
> + dc->realize = bcm2836_realize;
> +
> + /*
> + * Reason: creates an ARM CPU, thus use after free(), see
> + * arm_cpu_class_init()
> + */
> + dc->cannot_destroy_with_object_finalize_yet = true;
> +}
> +
> +static const TypeInfo bcm2836_type_info = {
> + .name = TYPE_BCM2836,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(BCM2836State),
> + .instance_init = bcm2836_init,
> + .class_init = bcm2836_class_init,
> +};
> +
> +static void bcm2836_register_types(void)
> +{
> + type_register_static(&bcm2836_type_info);
> +}
> +
> +type_init(bcm2836_register_types)
> diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
> new file mode 100644
> index 0000000..cd0fd02
> --- /dev/null
> +++ b/include/hw/arm/bcm2836.h
> @@ -0,0 +1,34 @@
> +/*
> + * Raspberry Pi emulation (c) 2012 Gregory Estrade
> + * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
> + *
> + * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
> + * Written by Andrew Baumann
> + *
> + * This code is licensed under the GNU GPLv2 and later.
> + */
> +
> +#ifndef BCM2836_H
> +#define BCM2836_H
> +
> +#include "hw/arm/arm.h"
> +#include "hw/arm/bcm2835_peripherals.h"
> +#include "hw/intc/bcm2836_control.h"
> +
> +#define TYPE_BCM2836 "bcm2836"
> +#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
> +
> +#define BCM2836_NCPUS 4
> +
> +typedef struct BCM2836State {
> + /*< private >*/
> + DeviceState parent_obj;
> + /*< public >*/
> +
> + uint32_t enabled_cpus;
blank line here.
Otherwise,
Reviewed-by: Peter Crosthwaite <address@hidden>
Regards,
Peter
> + ARMCPU cpus[BCM2836_NCPUS];
> + BCM2836ControlState control;
> + BCM2835PeripheralState peripherals;
> +} BCM2836State;
> +
> +#endif /* BCM2836_H */
> --
> 2.5.3
>
- [Qemu-devel] [PATCH v4 1/8] bcm2835_mbox: add BCM2835 mailboxes, (continued)
[Qemu-devel] [PATCH v4 6/8] bcm2836: add bcm2836 soc device, Andrew Baumann, 2016/01/15
- Re: [Qemu-devel] [PATCH v4 6/8] bcm2836: add bcm2836 soc device,
Peter Crosthwaite <=
[Qemu-devel] [PATCH v4 5/8] bcm2836_control: add bcm2836 ARM control logic, Andrew Baumann, 2016/01/15
[Qemu-devel] [PATCH v4 7/8] arm/boot: move highbank secure board setup code to common routine, Andrew Baumann, 2016/01/15
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