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[Qemu-devel] [PATCH 6/9] hw/mips: implement ITC Storage - Bypass View
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 6/9] hw/mips: implement ITC Storage - Bypass View |
Date: |
Wed, 3 Feb 2016 16:56:48 +0000 |
Bypass View does not cause issuing thread to block and does not affect
any of the cells state bit.
Read from a FIFO cell returns the value of the oldest entry.
Store to a FIFO cell changes the value of the newest entry.
Signed-off-by: Leon Alrae <address@hidden>
---
hw/misc/mips_itu.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index dd10b11..55241af 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -174,6 +174,27 @@ static void QEMU_NORETURN
block_thread_and_exit(ITCStorageCell *c)
cpu_loop_exit(current_cpu);
}
+/* ITC Bypass View */
+
+static inline uint64_t view_bypass_read(ITCStorageCell *c)
+{
+ if (c->tag.FIFO) {
+ return c->data[c->fifo_out];
+ } else {
+ return c->data[0];
+ }
+}
+
+static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
+{
+ if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
+ int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
+ c->data[idx] = val;
+ }
+
+ /* ignore a write to the semaphore cell */
+}
+
/* ITC Control View */
static inline uint64_t view_control_read(ITCStorageCell *c)
@@ -340,6 +361,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr,
unsigned size)
uint64_t ret = -1;
switch (view) {
+ case ITCVIEW_BYPASS:
+ ret = view_bypass_read(cell);
+ break;
case ITCVIEW_CONTROL:
ret = view_control_read(cell);
break;
@@ -372,6 +396,9 @@ static void itc_storage_write(void *opaque, hwaddr addr,
uint64_t data,
ITCView view = get_itc_view(addr);
switch (view) {
+ case ITCVIEW_BYPASS:
+ view_bypass_write(cell, data);
+ break;
case ITCVIEW_CONTROL:
view_control_write(cell, data);
break;
--
2.1.0
- [Qemu-devel] [PATCH 0/9] mips: implement Inter-Thread Communication Unit, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 1/9] hw/mips: implement ITC Configuration Tags, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 2/9] hw/mips: add ITC Storage Cells, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 3/9] hw/mips: implement ITC Storage - Control View, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 4/9] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 5/9] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 8/9] target-mips: check CP0 enabled for CACHE instruction also in R6, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 6/9] hw/mips: implement ITC Storage - Bypass View,
Leon Alrae <=
- [Qemu-devel] [PATCH 7/9] hw/mips_malta: make ITU available to multi-threading processors, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 9/9] target-mips: make ITC Configuration Tags accessible to the CPU, Leon Alrae, 2016/02/03