Re: [Qemu-devel] [PATCH] target-arm: Fix MDCCSR_EL0 instruction encoding

[Peter Maydell]

On 9 February 2016 at 20:57, Dirk Müller <address@hidden> wrote:
> See C5.1.5 of the ARMv8 Reference Manual
>
> Signed-off-by: Dirk Mueller <address@hidden>
> ---
>  target-arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 5ea507f..954e6e8 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3682,7 +3682,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
>       * We don't implement the configurable EL0 access.
>       */
>      { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
> -      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
> +      .cp = 14, .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
>        .type = ARM_CP_ALIAS,
>        .access = PL1_R,
>        .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },

Hi; you're right that we have the wrong encoding for the AArch64
register here, but this change would break the AArch32 version
(which is at cp14, 0, c0, c1, 0). You need to split the regdef
into two, one for AArch64 and one for AArch32.

thanks
-- PMM