Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

[Jean-Christophe DUBOIS]

Le 16/02/2016 22:06, Peter Maydell a écrit :
> On 16 February 2016 at 20:49, Jean-Christophe DUBOIS
> <address@hidden> wrote:
> > Le 16/02/2016 16:31, Peter Maydell a écrit :
> > > On 8 February 2016 at 22:08, Jean-Christophe Dubois <address@hidden>
> > > wrote:
> > > > +        object_property_set_bool(OBJECT(&s->cpu[i]), false,
> > > > +                                 "has_el3", &error_abort);
> > > Do the CPUs in this board really not have EL3 ?
> >
> > Well the Cortex A9 is certainly able to get to the secure mode. However, if
> > I enable it (has_el3 set to true), the OS (Linux or Xvisor) will not boot.
> > Disabling it allow both OS to boot on the emulated i.MX6.
> >
> > Would you have some idea on the reason for this "hang" during the boot when
> > EL3 is enabled?
> How are you booting the OS/hypervisor? Via -kernel or via -bios ?

via -kernel ...

> Usually if it doesn't boot this is because there's some bit of
> boot rom/loader code that runs on the real h/w and isn't being
> run in your QEMU setup, that does the initial setup of the h/w
> in secure mode. (In particular, if the secure side doesn't set
> the GIC interrupts to be NS accessible then things don't work
> very well.)

Well I guess on real hw uboot is setting things so that everything work 
thereafter. But here I don't have uboot and I jump directly to Linux ...

In QEMU, other Cortex A9 (Versatilepb.c, Exynos, Zynq ...) are also 
setting has_el3 to false ...

JC
> I wouldn't have expected that to be an issue for booting linux
> via -kernel though because there we should be booting the kernel
> NS and have a hack to configure the GIC appropriately.
>
> Peter C may remember the details of how this should work
> better than me.
>
> thanks
> -- PMM