[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 4/8] mips/kvm: Support unsigned KVM registers
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 4/8] mips/kvm: Support unsigned KVM registers |
Date: |
Fri, 26 Feb 2016 11:16:56 +0000 |
From: James Hogan <address@hidden>
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/kvm.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index 57cde9d..abdd6b6 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
@@ -248,6 +248,17 @@ static inline int kvm_mips_put_one_reg(CPUState *cs,
uint64_t reg_id,
return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
}
+static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id,
+ uint32_t *addr)
+{
+ struct kvm_one_reg cp0reg = {
+ .id = reg_id,
+ .addr = (uintptr_t)addr
+ };
+
+ return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
+}
+
static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
target_ulong *addr)
{
@@ -282,6 +293,17 @@ static inline int kvm_mips_get_one_reg(CPUState *cs,
uint64_t reg_id,
return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
}
+static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id,
+ uint32_t *addr)
+{
+ struct kvm_one_reg cp0reg = {
+ .id = reg_id,
+ .addr = (uintptr_t)addr
+ };
+
+ return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
+}
+
static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id,
target_ulong *addr)
{
--
2.1.0
- [Qemu-devel] [PULL 0/8] target-mips queue, Leon Alrae, 2016/02/26
- [Qemu-devel] [PULL 1/8] mips/kvm: Remove a couple of noisy DPRINTFs, Leon Alrae, 2016/02/26
- [Qemu-devel] [PULL 2/8] mips/kvm: Implement PRid CP0 register, Leon Alrae, 2016/02/26
- [Qemu-devel] [PULL 3/8] mips/kvm: Implement Config CP0 registers, Leon Alrae, 2016/02/26
- [Qemu-devel] [PULL 4/8] mips/kvm: Support unsigned KVM registers,
Leon Alrae <=
- [Qemu-devel] [PULL 7/8] mips/kvm: Support MSA in MIPS KVM guests, Leon Alrae, 2016/02/26
- [Qemu-devel] [PULL 6/8] mips/kvm: Support FPU in MIPS KVM guests, Leon Alrae, 2016/02/26
- [Qemu-devel] [PULL 5/8] mips/kvm: Support signed 64-bit KVM registers, Leon Alrae, 2016/02/26
- [Qemu-devel] [PULL 8/8] target-mips: implement R6 multi-threading, Leon Alrae, 2016/02/26
- Re: [Qemu-devel] [PULL 0/8] target-mips queue, Peter Maydell, 2016/02/26