Re: [Qemu-devel] [Qemu-ppc] [PATCH 72/77] ppc: A couple more dummy POWER8 Book4 regs

[Thomas Huth]

On 11.03.2016 15:22, Cédric Le Goater wrote:
> On 03/11/2016 11:04 AM, Thomas Huth wrote:
>> On 10.03.2016 23:27, Cédric Le Goater wrote:
>>> On 03/10/2016 07:01 PM, Thomas Huth wrote:
>>>> On 09.03.2016 22:17, Thomas Huth wrote:
>>>>> On 09.03.2016 21:04, Cédric Le Goater wrote:
>>>> ....
>>>>>> I have been maintaining a port of Ben's patchset on the latest qemu for 
>>>>>> other 
>>>>>> parts which should come after pnv is merged so I have a framework to 
>>>>>> test such 
>>>>>> sub-patchsets. I also have time to work on them but clearly not the 
>>>>>> expertise
>>>>>> in all areas !
>>>>>
>>>>> That would be great if you could take care of this!
>>>>>
>>>>>> What would be nice is to identify the most obvious ones, non 
>>>>>> controversial
>>>>>> that could be merged after a few iterations. I have a vague idea, the 
>>>>>> ones 
>>>>>> Reviewed-by David obviously being good candidates, the definition of new 
>>>>>> SPRs 
>>>>>> (even the dummy ones ?).
>>>>>
>>>>> I really like to see the KVM SPRs patches first - since they are fixing
>>>>> potential problems with migration of the _current_ KVM machines already!
>>>>> And being bug fixes, maybe these patches could even be included for QEMU
>>>>> 2.6 already? (i.e. before the hard freeze at the end of March)
>>>>>
>>>>> So my wish-list for a first small patch series looks like this:
>>>>>
>>>>> 5b287e66c7513209  ppc: Add macros to register hypervisor mode SPRs
>>>>> 34f1af75e75e7ba0  ppc: Add dummy CIABR SPR
>>>>> 48adf38e9cab4663  ppc: A couple more dummy POWER8 Book4 regs
>>>>> 730a9b4dc9414818  ppc: Add KVM numbers to some P8 SPRs
>>>>>
>>>>> There are a couple of other patches touching the SPRs initialization,
>>>>> but they are not important with regards to migration... so not sure
>>>>> whether it makes sense to include them now already...
>>>>
>>>> FWIW, I just saw today (by doing some more experiments with
>>>> kvm-unit-tests) that the IAMR register is also not migrated yet ... so
>>>> it would be nice if you could include the related patches for IAMR, too,
>>>> and wire the KVM part up with KVM_REG_PPC_IAMR...
>>>
>>> OK. So we should be targeting something like :
>>>
>>>     ppc: Update SPR definitions
>>>     ppc: Add macros to register hypervisor mode SPRs
>>>     ppc: Add a bunch of hypervisor SPRs to Book3s
>>>
>>>     ppc: LPCR is a HV resource
>>>     ppc: SPURR & PURR are HV writeable and privileged
>>>     ppc: Add dummy SPR_IC for POWER8
>>>     ppc: Initialize AMOR in PAPR mode
>>>     ppc: Fix writing to AMR/UAMOR
>>>     ppc: Add POWER8 IAMR register
>>>     ppc: Add a few more P8 PMU SPRs
>>>     ppc: Add dummy write to VTB
>>>     ppc: Add dummy POWER8 MPPR register
>>>     ppc: Add dummy POWER8 PSPB SPR
>>>     ppc: Add dummy CIABR SPR
>>>     ppc: Add dummy ACOP SPR
>>>     ppc: A couple more dummy POWER8 Book4 regs
>>>     ppc: Add KVM numbers to some P8 SPRs
>>
>> Sounds good - but you likely can drop the "Add a few more P8 PMU SPRs"
>> from your list since it has already been queued by David already (see
>> https://github.com/dgibson/qemu/commits/ppc-for-2.6), and the PSPB patch
>> is also not required anymore since I submitted a similar patch to David
>> already when I discovered that it is lost during migration.
> 
> Here is a first port on Dave's 2.6 branch. I tried to keep the
> patchset minimal but I had to pull a few extra patches to keep
> them more or less in sync with the original version from Ben.
> 
>       ppc: Update SPR definitions
>       ppc: Add macros to register hypervisor mode SPRs
>       ppc: Add a bunch of hypervisor SPRs to Book3s
>       ppc: Add number of threads per core to the processor definition
>       ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
>       ppc: Create cpu_ppc_set_papr() helper
>       ppc: Better figure out if processor has HV mode
>       ppc: Add placeholder SPRs for DPDES and DHDES on P8
>       ppc: SPURR & PURR are HV writeable and privileged
>       ppc: Add dummy SPR_IC for POWER8
>       ppc: Initialize AMOR in PAPR mode
>       ppc: Fix writing to AMR/UAMOR
>       ppc: Add POWER8 IAMR register
>       ppc: Add dummy write to VTB
>       ppc: Add dummy POWER8 MPPR register
>       ppc: Add dummy CIABR SPR
>       ppc: Add dummy ACOP SPR
>       ppc: A couple more dummy POWER8 Book4 regs
>       ppc: Add KVM numbers to some P8 SPRs
> 
> Available here:
> 
>       https://github.com/legoater/qemu/commits/for-2.6
> 
> If you want to take a look, I did some quick test on KVM and
> TCG on a ppc64le ubuntu host but no migration.
> 
> These two will probably need a merge as the first breaks the
> compile, and I modified the second.
> 
>       ppc: Fix writing to AMR/UAMOR
>       ppc: Add POWER8 IAMR register

Modifying patches is fine as long as you mention the changes in the
patch description (in square brackets) and add your Sob - looking at
your tree, you already did this for the "ppc: Add POWER8 IAMR register"
patch, so that should be OK.

I'd maybe also squash the "Add KVM numbers to some P8 SPRs" patch into
the "Add a bunch of hypervisor SPRs to Book3s" to reduce the code churn
a little bit (note that the patch description for the "Add a bunch of
hypervisor SPRs to Book3s" patch is misleading - DAWR and DAWRX need to
be synchronized for migration, since the guest can set this register via
the H_SET_MODE hypercall).

You could maybe also merge "Add dummy ACOP SPR" with "A couple more
dummy POWER8 Book4 regs" since the latter patch completely reworks the
definition of the ACOP register.

 Thomas